diff options
| author | Marc Jones <marc.jones@amd.com> | 2008-07-12 00:03:26 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2008-07-12 00:03:26 +0000 |
| commit | 2c39c4c5a9cf767eaf92d5961c3fd2e7b60811b4 (patch) | |
| tree | 466cfd91559a3fa7381609522b7f5e2ee00732ce /src/southbridge/amd/cs5536 | |
| parent | 2f45e770d7a16a37d6667dc3bd4a8c1a51cfbbe5 (diff) | |
There was a programming error which made most USB port4 setup wrong. This patch uses byte pointer and the MMIO read and write functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536')
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 30 |
1 files changed, 16 insertions, 14 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 5c827f275f..51e9c6f788 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -409,7 +409,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint32_t *bar; + uint8_t *bar; msr_t msr; device_t dev; @@ -425,32 +425,33 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /* write to clear diag register */ wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Make HCCPARAMS writeable */ - *(bar + IPREG04) |= USB_HCCPW_SET; + writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04); /* ; EECP=50h, IST=01h, ASPC=1 */ - *(bar + HCCPARAMS) = 0x00005012; + writel(0x00005012, bar + HCCPARAMS); } dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - *(bar + UOCMUX) &= PUEN_SET; + writel(readl(bar + UOCMUX) & PUEN_SET, bar + UOCMUX); /* Host or Device? */ if (sb->enable_USBP4_device) { - *(bar + UOCMUX) |= PMUX_DEVICE; + writel(readl(bar + UOCMUX) | PMUX_DEVICE, bar + UOCMUX); } else { - *(bar + UOCMUX) |= PMUX_HOST; + writel(readl(bar + UOCMUX) | PMUX_HOST, bar + UOCMUX); } /* Overcurrent configuration */ if (sb->enable_USBP4_overcurrent) { - *(bar + UOCCAP) |= sb->enable_USBP4_overcurrent; + writel(readl(bar + UOCCAP) + | sb->enable_USBP4_overcurrent, bar + UOCCAP); } } @@ -464,19 +465,20 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - *(bar + UDCDEVCTL) |= UDC_SD_SET; + writel(readl(bar + UDCDEVCTL) | UDC_SD_SET, + bar + UDCDEVCTL); } dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - *(bar + UOCCTL) |= PADEN_SET; - *(bar + UOCCAP) |= APU_SET; + writel(readl(bar + UOCCTL) | PADEN_SET, bar + UOCCTL); + writel(readl(bar + UOCCAP) | APU_SET, bar + UOCCAP); } } |