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authorStefan Reinauer <stepan@coresystems.de>2010-04-21 20:06:10 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-21 20:06:10 +0000
commit9839cbd53fdcfcee52c406d9f52af924192e618d (patch)
treea38daaa0b545aaf36a7ad5f5df9dfe73e08d97da /src/southbridge/amd/cs5536/cs5536.h
parentcf036d1266d7ec307aac437105b094acbc9681ec (diff)
* clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M) * call void main(unsigned long bist) except void cache_as_ram_main(void) on Geode LX (as we do on almost all other platforms now) * Unify Geode LX MSR setup (will bring most non-working LX targets back to life) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/cs5536.h')
-rw-r--r--src/southbridge/amd/cs5536/cs5536.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h
index a00709a4a9..073bb3ea59 100644
--- a/src/southbridge/amd/cs5536/cs5536.h
+++ b/src/southbridge/amd/cs5536/cs5536.h
@@ -464,4 +464,13 @@
#define FLASH_IO_128B 0x0000FF80
#define FLASH_IO_256B 0x0000FF00
+#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
+void cs5536_setup_onchipuart(int uart);
+void cs5536_disable_internal_uart(void);
+#else
+void chipsetinit(void);
+#endif
+#endif
+
#endif /* _CS5536_H */