These changes incorporate steve goodrich'es fixes, and one bug that is

disabled. 

cs5536: add new entires for SB  control etc. 
cs5536.c: chip_enabled function moved to chip_init, so it only gets run
once.
IRQ setup improved
gx2def.h: new defines added
vr.h: new file, with new def's for virtual register control. 
mainboard config.lb: new entries added for nb and sb control.
chipsetinit.c: new controls added -- I forget all the details :-)
grphinit.c: new function added
northbridge.c: new IRQ control added. FlashChipSetup added, controlled
by chip info setupflash struct member. Currently, if enabled, this hangs
OLPC in linux PCI scan.
chip.h: new struct members added for unwanted device enable, flash setup 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 45 insertions, 22 deletions

diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index d5d0ae8255..9dcffd6fbc 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -9,22 +9,19 @@
 #include <cpu/x86/msr.h>
 #include "chip.h"
 
-static void southbridge_init(struct device *dev)
-{
-	printk_err("cs5536: %s\n", __FUNCTION__);
-	setup_i8259(); 
-}
-
 
 #define PIN_OPT_IDE		(1ULL<<0)	/* 0 for flash, 1 for IDE */
 
 /* Intended value for LBAR_FLSH0: 4KiB, enabled, MMIO, NAND, @0x20000000 */
+/* NOTE: no longer used, prune at some point */
 msr_t flsh0 = { .hi=0xFFFFF007, .lo=0x20000000};
 
 static void
 enable_ide_nand_flash(){
 	msr_t msr;
 	printk_err("cs5536: %s\n", __FUNCTION__);
+#if 0
+	/* steve took this one out ... not sure if needed or not */
 	msr = rdmsr(MDD_LBAR_FLSH0);
 
 	if ( ((msr.hi) & 7) != 7) {
@@ -33,7 +30,7 @@ enable_ide_nand_flash(){
 	}
 	msr = rdmsr(MDD_LBAR_FLSH0);
 	printk_err("MDD_LBAR_FLSH0 is 0x%08x%08x\n", msr.hi,msr.lo);
-
+#endif
 	msr = rdmsr(MDD_PIN_OPT);
 	if (msr.lo & PIN_OPT_IDE) {
 		printk_err("MDD_PIN_OPT was 0x%08x%08x\n", msr.hi,msr.lo);
@@ -41,7 +38,7 @@ enable_ide_nand_flash(){
 		wrmsr(MDD_PIN_OPT, msr);
 	}
 	msr = rdmsr(MDD_PIN_OPT);
-	printk_err("MDD_LBAR_FLSH0 is 0x%08x%08x\n", msr.hi,msr.lo);
+	printk_err("MDD_PIN_OPT is 0x%08x%08x\n", msr.hi,msr.lo);
 
 	msr = rdmsr(MDD_NANDF_DATA);
 	if (msr.lo != 0x00100010) {
@@ -63,6 +60,7 @@ enable_ide_nand_flash(){
 	printk_err("cs5536: EXIT %s\n", __FUNCTION__);
 }
 
+#if 0
 /* note: this is a candidate for inclusion in src/devices/pci_device.c */
 void
 setup_irq(unsigned irq, char *name, unsigned level, unsigned bus, unsigned device, unsigned fn){
@@ -78,17 +76,23 @@ setup_irq(unsigned irq, char *name, unsigned level, unsigned bus, unsigned devic
 			printk_err("%s: Can't find %s at 0x%x\n", __FUNCTION__, name, devfn);
 	}
 }
+#endif
 
-static void southbridge_enable(struct device *dev)
+static void southbridge_init(struct device *dev)
 {
 	struct southbridge_amd_cs5536_config  *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
-	msr_t msr;
+	const unsigned char slots_cpu[4] = {11, 0, 0, 0};
+	const unsigned char slots_sb[4] = {11, 5, 10, 10};
+ 	msr_t msr;
+	int i;
 	/*
 	 * struct device *gpiodev;
 	 * unsigned short gpiobase = MDD_GPIO;
 	 */
 
-	printk_err("%s: dev is %p\n", __FUNCTION__, dev);
+	printk_err("cs5536: %s\n", __FUNCTION__);
+	setup_i8259(); 
+
 	if (sb->lpc_serirq_enable) {
 		msr.lo = sb->lpc_serirq_enable;
 		msr.hi  = 0;
@@ -114,30 +118,49 @@ static void southbridge_enable(struct device *dev)
 	}
 
 	if (sb->enable_uarta){
-		printk_err("%s: enable uarta, msr MDD_IRQM_YHIGH(%x) \n",
+		printk_err("cs5536: %s: enable uarta, msr MDD_IRQM_YHIGH(%x) \n",
 				 __FUNCTION__, MDD_IRQM_YHIGH);
 		msr = rdmsr(MDD_IRQM_YHIGH);
 		msr.lo |= 0x04000000;
 		wrmsr(MDD_IRQM_YHIGH, msr);
 	}
 
-	printk_err("%s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
+	printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
 	if (sb->enable_ide_nand_flash) {
 		enable_ide_nand_flash();
 	}
 
-	/* irq handling */
-	setup_irq(sb->audio_irq, "audio", 1, 0, 0xf, 2);
-	setup_irq(sb->usbf4_irq, "usb f4", 1, 0, 0xf, 4);
-	setup_irq(sb->usbf5_irq, "usb f5", 1, 0, 0xf, 5);
-	setup_irq(sb->usbf6_irq, "usb f6", 1, 0, 0xf, 6);
-	setup_irq(sb->usbf7_irq, "usb f7", 1, 0, 0xf, 7);
-	
+#if 0
+ 	/* irq handling */
+ 	setup_irq(sb->audio_irq, "audio", 1, 0, 0xf, 2);
+ 	setup_irq(sb->usbf4_irq, "usb f4", 1, 0, 0xf, 4);
+ 	setup_irq(sb->usbf5_irq, "usb f5", 1, 0, 0xf, 5);
+ 	setup_irq(sb->usbf6_irq, "usb f6", 1, 0, 0xf, 6);
+ 	setup_irq(sb->usbf7_irq, "usb f7", 1, 0, 0xf, 7);
+#else
+	/* CPU (80000800 = 00.01.00) */
+	pci_assign_irqs(0, 0x01, slots_cpu);	/* bus=0, device=0x01, slots={11,0,0,0} */
+ 	
+	/* Southbridge (80007800 = 00.0F.00) */
+	pci_assign_irqs(0, 0x0F, slots_sb);	/* bus=0, device=0x0F, slots={11,5,10,10} */
+#endif
+	/* disable unwanted virtual PCI devices */
+	for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
+		printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]);
+		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
+		outl(0xDEADBEEF,                  0xCFC);
+	}
 }
 
+
+static void southbridge_enable(struct device *dev)
+{
+	printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev);
+ }
+
 static void cs5536_pci_dev_enable_resources(device_t dev)
 {
-	printk_err("cs5536.c: %s()\n", __FUNCTION__);
+	printk_err("cs5536: %s()\n", __FUNCTION__);
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
 }
@@ -147,7 +170,7 @@ static struct device_operations southbridge_ops = {
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = cs5536_pci_dev_enable_resources,
 	.init             = southbridge_init,
-	.enable           = southbridge_enable,
+//	.enable           = southbridge_enable,
 	.scan_bus         = scan_static_bus,
 };