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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-25 19:40:20 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-25 19:40:20 +0000 |
| commit | 1c2f49e74aa254c7c415641002c0c2f52ed42a5c (patch) | |
| tree | 39d3b9203e94f00a574afc9fb3941232c7c41178 /src/southbridge/amd/cs5536/chip.h | |
| parent | 5ee2bbb90cdc079e3e598c1f20237a32eed43e04 (diff) | |
to give ollie a look.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5536/chip.h')
| -rw-r--r-- | src/southbridge/amd/cs5536/chip.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h index 3e9be9938e..cb3cbe1039 100644 --- a/src/southbridge/amd/cs5536/chip.h +++ b/src/southbridge/amd/cs5536/chip.h @@ -4,7 +4,10 @@ extern struct chip_operations southbridge_amd_cs5536_ops; struct southbridge_amd_cs5536_config { - int none; + /* interrupt enable for LPC bus */ + int lpc_serirq_enable; /* how to enable, e.g. 0x80 */ + int lpc_irq; /* what to enable, e.g. 0x18 */ + int enable_gpio0_inta; /* almost always will be true */ }; #endif /* _SOUTHBRIDGE_AMD_CS5536 */ |