src/southbridge: Code formating

Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

3 files changed, 11 insertions, 11 deletions

diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
index 05fb6eb1da..a6c0084087 100644
--- a/src/southbridge/amd/cs5535/chipsetinit.c
+++ b/src/southbridge/amd/cs5535/chipsetinit.c
@@ -328,7 +328,7 @@ chipsetinit(void)
 	i = 0;
 
 	csi = &SB_MASTER_CONF_TABLE[i];
-	for(; csi->msrnum; csi++){
+	for (; csi->msrnum; csi++){
 		msr.lo = csi->msr.lo;
 		msr.hi = csi->msr.hi;
 		wrmsr(csi->msrnum, msr); // MSR - see table above
@@ -347,7 +347,7 @@ chipsetinit(void)
 	{
 		csi = CS5535_CLOCK_GATING_TABLE;
 
-		for(; csi->msrnum; csi++){
+		for (; csi->msrnum; csi++){
 			msr.lo = csi->msr.lo;
 			msr.hi = csi->msr.hi;
 			wrmsr(csi->msrnum, msr);	// MSR - see table above
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 70b8386dfa..3f6e48ff55 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -56,9 +56,9 @@ static void dump_south(struct device *dev)
 {
 	int i, j;
 
-	for(i=0; i<256; i+=16) {
+	for (i=0; i<256; i+=16) {
 		printk(BIOS_DEBUG, "0x%02x: ", i);
-		for(j=0; j<16; j++)
+		for (j=0; j<16; j++)
 			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
 		printk(BIOS_DEBUG, "\n");
 	}
@@ -103,9 +103,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = {
 };
 
 struct chip_operations southbridge_amd_cs5535_ops = {
-        CHIP_NAME("AMD Geode CS5535 Southbridge")
-            /* This is only called when this device is listed in the
-             * static device tree.
-             */
-            .enable_dev = southbridge_enable,
+	CHIP_NAME("AMD Geode CS5535 Southbridge")
+	    /* This is only called when this device is listed in the
+	     * static device tree.
+	     */
+	    .enable_dev = southbridge_enable,
 };
diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
index 1030aa0e88..935153f513 100644
--- a/src/southbridge/amd/cs5535/early_setup.c
+++ b/src/southbridge/amd/cs5535/early_setup.c
@@ -34,7 +34,7 @@ static void cs5535_setup_idsel(void)
 	outl(0x1 << (CS5535_DEV_NUM + 10), 0);
 }
 
-static void cs5535_usb_swapsif(void)
+static void cs5535_usb_swapsif (void)
 {
 	msr_t msr;
 
@@ -133,7 +133,7 @@ static void cs5535_early_setup(void)
 	printk(BIOS_DEBUG, "Setup idsel\n");
 	cs5535_setup_idsel();
 	printk(BIOS_DEBUG, "Setup iobase\n");
-	cs5535_usb_swapsif();
+	cs5535_usb_swapsif ();
 	cs5535_setup_iobase();
 	printk(BIOS_DEBUG, "Setup gpio\n");
 	cs5535_setup_gpio();