diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-16 20:53:49 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-17 16:55:44 +0100 |
| commit | 55e31a9e335943ef26d182ade53103df367e8745 (patch) | |
| tree | 1505b4bccfc7c1f93d8f5a96420c88cf0ed06a9a /src/southbridge/amd/cs5535 | |
| parent | dcf253c74e3eb88e738f425c9a9bfd897736c2b0 (diff) | |
southbridge/amd amd81XX, cs553X & sr5650 spelling fixes
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7842
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/amd/cs5535')
| -rw-r--r-- | src/southbridge/amd/cs5535/chipsetinit.c | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5535/cs5535.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index fd4c4ba440..ab1b640a44 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -116,7 +116,7 @@ static void pmChipsetInit(void) /* GPIO24 is setup in preChipsetInit for two reasons * 1. GPIO24 at reset defaults to disabled, since this signal is * vsb_work_aux on Hawk it controls the FET's for all voltage - * rails except Vstanby & Vmem. BIOS needs to enable GPIO24 as + * rails except Vstandby & Vmem. BIOS needs to enable GPIO24 as * OUT_AUX1 & OUTPUT_EN early so it is driven by 5535. * 2. Non-PM builds will require GPIO24 enabled for instant-off power * button @@ -127,7 +127,7 @@ static void pmChipsetInit(void) * On Hawk, GPIO11 is connected to control input of external clock * generator for 14MHz, PCI, USB & LPC clocks. * Programming of GPIO11 will be done by VSA PM code. During VSA - * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks + * Init. BIOS writes PM Core Virtual Register indicating if S1 Clocks * should be On or Off. This is based on a Setup item. We do not want * to leave GPIO11 enabled because of a Hawk board problem. With * GPIO11 enabled in S3, something is back-driving GPIO11 causing it diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 42707c049c..e66a1e2926 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -20,7 +20,7 @@ static void nvram_on(struct device *dev) pci_write_config8(dev, 0x52, 0xee); /* Set positive decode on ROM */ - /* Also, there is no apparent reason to turn off the devoce on the */ + /* Also, there is no apparent reason to turn off the device on the */ /* IDE devices */ reg = pci_read_config8(dev, 0x5b); |