diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-10-07 14:36:16 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-10-07 14:36:16 +0000 |
commit | 31f81a6de1515df2eebcf6e1b1afd545fc7a2714 (patch) | |
tree | 3ab6e3da26b92933db7a5625c5df46845270415e /src/southbridge/amd/cs5530/cs5530_enable_rom.c | |
parent | fdfaada706037287c74e2541a6151f16d93b9be1 (diff) |
Enable full ROM access on AMD CS5530(A) (needed for CBFS).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cs5530/cs5530_enable_rom.c')
-rw-r--r-- | src/southbridge/amd/cs5530/cs5530_enable_rom.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5530/cs5530_enable_rom.c b/src/southbridge/amd/cs5530/cs5530_enable_rom.c new file mode 100644 index 0000000000..09ec3ed791 --- /dev/null +++ b/src/southbridge/amd/cs5530/cs5530_enable_rom.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "cs5530.h" + +static void cs5530_enable_rom(void) +{ + uint8_t reg8; + + /* So far all CS5530(A) ISA bridges we've seen are at 00:12.0. */ + device_t dev = PCI_DEV(0, 0x12, 0); + + /* + * Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and + * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. + * + * Make the ROM write-protected. + */ + reg8 = pci_read_config8(dev, ROM_AT_LOGIC_CONTROL_REG); + reg8 |= LOWER_ROM_ADDRESS_RANGE; + reg8 |= UPPER_ROM_ADDRESS_RANGE; + reg8 &= ~ROM_WRITE_ENABLE; + pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); + + /* Set positive decode on ROM. */ + reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2); + reg8 |= BIOS_ROM_POSITIVE_DECODE; + pci_write_config8(dev, DECODE_CONTROL_REG2, reg8); +} |