diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2019-12-05 17:35:00 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-16 09:42:32 +0000 |
| commit | 45d05d08237e5c262312453a2f272ef32d9366fb (patch) | |
| tree | 54edce2a66f1d69272539c72f8afce0463c9555f /src/southbridge/amd/common | |
| parent | bf15b2f7c3474c9811516d16f40a3533da5108c7 (diff) | |
ec/google/chromeec/acpi: move PS2K under PCI0
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node]
moved the PS2K ACPI device from under the SIO device to under
the LPCB, and while this fixed the keyboard under Windows for
Skylake devices, it was insufficient for Baytrail and Braswell
devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional
under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW,
BYT, SKL, BSW, and KBL platforms, verify keyboard functional
under both Linux (4.x and 5.x) and Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/common')
0 files changed, 0 insertions, 0 deletions