x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

4 files changed, 20 insertions, 17 deletions

diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index b0ec2dcb2e..1e1357eba8 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -237,12 +237,12 @@ static void sb700_enable(device_t dev)
 				u32 ioapic_base;
 				printk(BIOS_DEBUG, "sm_init().\n");
 				ioapic_base = IO_APIC_ADDR;
-				clear_ioapic(ioapic_base);
+				clear_ioapic((void *)ioapic_base);
 				/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 				if (CONFIG_MAX_CPUS >= 16)
-					setup_ioapic(ioapic_base, 0);
+					setup_ioapic((void *)ioapic_base, 0);
 				else
-					setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
+					setup_ioapic((void *)ioapic_base, CONFIG_MAX_CPUS + 1);
 			}
 			break;
 
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 510bf234fb..e01793607b 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -353,18 +353,19 @@ static void sb800_enable(device_t dev)
 		break;
 
 	case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
-		clear_ioapic(IO_APIC_ADDR);
+		clear_ioapic(VIO_APIC_VADDR);
 #if CONFIG_CPU_AMD_AGESA
 		/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
-		setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+		setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 #else
 		/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
 		/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
-		setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+		setup_ioapic(VIO_APIC_VADDR,
+			     CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
 #elif (CONFIG_APIC_ID_OFFSET > 0)
 		/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
-		setup_ioapic(IO_APIC_ADDR, 0);
+		setup_ioapic(VIO_APIC_VADDR, 0);
 #else
 #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
 #endif
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index c84eee20c2..48820bc2bb 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -40,15 +40,17 @@ static u32 spibar;
 static void reset_internal_fifo_pointer(void)
 {
 	do {
-		write8(spibar + 2, read8(spibar + 2) | 0x10);
-	} while (read8(spibar + 0xD) & 0x7);
+		write8((void *)(spibar + 2),
+		       read8((void *)(spibar + 2)) | 0x10);
+	} while (read8((void *)(spibar + 0xD)) & 0x7);
 }
 
 static void execute_command(void)
 {
-	write8(spibar + 2, read8(spibar + 2) | 1);
+	write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
 
-	while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
+	while ((read8((void *)(spibar + 2)) & 1) &&
+	       (read8((void *)(spibar+3)) & 0x80));
 }
 
 void spi_init()
@@ -91,12 +93,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 	readoffby1 = bytesout ? 0 : 1;
 
 	readwrite = (bytesin + readoffby1) << 4 | bytesout;
-	write8(spibar + 1, readwrite);
-	write8(spibar + 0, cmd);
+	write8((void *)(spibar + 1), readwrite);
+	write8((void *)(spibar + 0), cmd);
 
 	reset_internal_fifo_pointer();
 	for (count = 0; count < bytesout; count++, dout++) {
-		write8(spibar + 0x0C, *(u8 *)dout);
+		write8((void *)(spibar + 0x0C), *(u8 *)dout);
 	}
 
 	reset_internal_fifo_pointer();
@@ -105,12 +107,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 	reset_internal_fifo_pointer();
 	/* Skip the bytes we sent. */
 	for (count = 0; count < bytesout; count++) {
-		cmd = read8(spibar + 0x0C);
+		cmd = read8((void *)(spibar + 0x0C));
 	}
 
 	reset_internal_fifo_pointer();
 	for (count = 0; count < bytesin; count++, din++) {
-		*(u8 *)din = read8(spibar + 0x0C);
+		*(u8 *)din = read8((void *)(spibar + 0x0C));
 	}
 
 	return 0;
diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h
index 7a61569992..b6bde9fdd5 100644
--- a/src/southbridge/amd/cimx/sb900/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h
@@ -3,7 +3,7 @@
 
 /* Hudson-2 ACPI PmIO Space Define */
 #define SB_ACPI_BASE_ADDRESS              0x0400
-#define ACPI_MMIO_BASE  0xFED80000
+#define ACPI_MMIO_BASE  ((u8 *)0xFED80000)
 #define SB_CFG_BASE     0x000   // DWORD
 #define GPIO_BASE       0x100   // BYTE
 #define SMI_BASE        0x200   // DWORD