src: Get rid of unneeded whitespace

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

3 files changed, 19 insertions, 19 deletions

diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
index 816988b53e..6f0826fee4 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
@@ -178,7 +178,7 @@ Method(_INI, 0) {
 
 	/* On older chips, clear PciExpWakeDisEn */
 	/*if (LLessEqual(\SBRI, 0x13)) {
-	*    	Store(0,\PWDE)
+	*	Store(0,\PWDE)
 	* }
 	*/
 } /* End Method(_SB._INI) */
@@ -298,9 +298,9 @@ Scope(\){
 		PWMK, 1,
 		PWNS, 1,
 
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
+		/*	Offset(0x61), */	/*  Options_1 */
+		/*		,7,  */
+		/*		R617,1, */
 
 		Offset(0x65),	/* UsbPMControl */
 		, 4,
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index ebc6ba1f8d..29a1336f13 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -28,7 +28,7 @@
 #include <arch/acpi.h>
 #include <device/pci_ehci.h>
 #include "lpc.h"		/* lpc_read_resources */
-#include "SBPLATFORM.h" 	/* Platform Specific Definitions */
+#include "SBPLATFORM.h"		/* Platform Specific Definitions */
 #include "cfg.h"		/* sb800 Cimx configuration */
 #include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
 #include "sb_cimx.h"		/* AMD CIMX wrapper entries */
@@ -352,13 +352,13 @@ static void sb800_enable(struct device *dev)
 	switch (dev->path.pci.devfn) {
 	case PCI_DEVFN(0x11, 0): /* 0:11.0  SATA */
 		if (dev->enabled) {
-  			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
+			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
 			if (1 == sb_chip->boot_switch_sata_ide)
 				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 			else if (0 == sb_chip->boot_switch_sata_ide)
 				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 		} else {
-  			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
+			sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
 		}
 		break;
 
@@ -387,11 +387,11 @@ static void sb800_enable(struct device *dev)
 
 	case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */
 		if (dev->enabled) {
-  			if (AZALIA_DISABLE == sb_config->AzaliaController) {
-  				sb_config->AzaliaController = AZALIA_AUTO;
+			if (AZALIA_DISABLE == sb_config->AzaliaController) {
+				sb_config->AzaliaController = AZALIA_AUTO;
 			}
 		} else {
-  			sb_config->AzaliaController = AZALIA_DISABLE;
+			sb_config->AzaliaController = AZALIA_DISABLE;
 		}
 		break;
 
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index e792fe3c61..158e3f4a1e 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -25,8 +25,8 @@
 #include <device/pci_ehci.h>
 #include <arch/acpi.h>
 #include "lpc.h"		/* lpc_read_resources */
-#include "SbPlatform.h" 	/* Platform Specific Definitions */
-#include "chip.h" 		/* struct southbridge_amd_cimx_sb900_config */
+#include "SbPlatform.h"		/* Platform Specific Definitions */
+#include "chip.h"		/* struct southbridge_amd_cimx_sb900_config */
 
 #ifndef _RAMSTAGE_
 #define _RAMSTAGE_
@@ -353,13 +353,13 @@ static void sb900_enable(struct device *dev)
 
 	case (0x11 << 3) | 0: /* 0:11.0  SATA */
 		if (dev->enabled) {
-  			sb_config->SATAMODE.SataMode.SataController = ENABLED;
+			sb_config->SATAMODE.SataMode.SataController = ENABLED;
 			if (1 == sb_chip->boot_switch_sata_ide)
 				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 			else if (0 == sb_chip->boot_switch_sata_ide)
 				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 		} else {
-  			sb_config->SATAMODE.SataMode.SataController = DISABLED;
+			sb_config->SATAMODE.SataMode.SataController = DISABLED;
 		}
 
 //-		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
@@ -380,19 +380,19 @@ static void sb900_enable(struct device *dev)
 		if (dev->enabled) {
 			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
 		} else {
-  			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
+			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
 		}
 //-		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 		break;
 
 	case (0x14 << 3) | 2: /* 0:14:2 HDA */
 		if (dev->enabled) {
-  			if (AZALIA_DISABLE == sb_config->AzaliaController) {
-  				sb_config->AzaliaController = AZALIA_AUTO;
+			if (sb_config->AzaliaController == AZALIA_DISABLE) {
+				sb_config->AzaliaController = AZALIA_AUTO;
 			}
 			printk(BIOS_DEBUG, "hda enabled\n");
 		} else {
-  			sb_config->AzaliaController = AZALIA_DISABLE;
+			sb_config->AzaliaController = AZALIA_DISABLE;
 			printk(BIOS_DEBUG, "hda disabled\n");
 		}
 //-		azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
@@ -446,7 +446,7 @@ static void sb900_enable(struct device *dev)
 
 	/* Special setting ABCFG registers before PCI emulation. */
 //-	abSpecialSetBeforePciEnum(sb_config);
-//-  	usbDesertPll(sb_config);
+//-	usbDesertPll(sb_config);
 	//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
 	//AmdSbDispatcher(sb_config);
 }