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authorStefan Reinauer <reinauer@chromium.org>2011-10-31 12:56:45 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2011-11-01 19:07:45 +0100
commit5ff7c13e858a31addf1558731a12cf6c753b576d (patch)
tree82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src/southbridge/amd/cimx
parent784544b934d67dc85ccfcf33e04ff148045836ad (diff)
remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/cimx')
-rw-r--r--src/southbridge/amd/cimx/sb800/SBPLATFORM.h14
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c4
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/Amd.h0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/AmdSbLib.h0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/SbEarly.h0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/SbPlatform.h0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/bootblock.c6
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/cbtypes.h0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/chip.h0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/chip_name.c0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/early.c2
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/late.c0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/lpc.c0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/lpc.h0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/smbus.c0
-rw-r--r--[-rwxr-xr-x]src/southbridge/amd/cimx/sb900/smbus.h0
16 files changed, 13 insertions, 13 deletions
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index d7317a23a2..db5343dff0 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -20,7 +20,7 @@
* ***************************************************************************
*
*/
-
+
#ifndef _AMD_SBPLATFORM_H_
#define _AMD_SBPLATFORM_H_
@@ -112,7 +112,7 @@ typedef union _PCI_ADDR {
*/
#define SB_CIMx_PARAMETER 0x02
-// Generic
+// Generic
#define cimSpreadSpectrumDefault TRUE
#define cimSpreadSpectrumTypeDefault 0x00 // Normal
#define cimHpetTimerDefault TRUE
@@ -121,7 +121,7 @@ typedef union _PCI_ADDR {
#define cimSpiFastReadEnableDefault 0x01 // Enable
#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
#define cimSioHwmPortEnableDefault FALSE
-// GPP/AB Controller
+// GPP/AB Controller
#define cimNbSbGen2Default TRUE
#define cimAlinkPhyPllPowerDownDefault TRUE
#define cimResetCpuOnSyncFloodDefault TRUE
@@ -129,13 +129,13 @@ typedef union _PCI_ADDR {
#define cimGppMemWrImproveDefault TRUE
#define cimGppPortAspmDefault FALSE
#define cimGppLaneReversalDefault FALSE
-#define cimGppPhyPllPowerDownDefault TRUE
+#define cimGppPhyPllPowerDownDefault TRUE
// USB Controller
#define cimUsbPhyPowerDownDefault FALSE
// GEC Controller
#define cimSBGecDebugBusDefault FALSE
#define cimSBGecPwrDefault 0x03
-// Sata Controller
+// Sata Controller
#define cimSataSetMaxGen2Default 0x00
#define cimSATARefClkSelDefault 0x10
#define cimSATARefDivSelDefault 0x80
@@ -143,11 +143,11 @@ typedef union _PCI_ADDR {
#define cimSataPortMultCapDefault TRUE
#define cimSataPscCapDefault 0x00 // Enable
#define cimSataSscCapDefault 0x00 // Enable
-#define cimSataFisBasedSwitchingDefault FALSE
+#define cimSataFisBasedSwitchingDefault FALSE
#define cimSataCccSupportDefault FALSE
#define cimSataClkAutoOffDefault FALSE
#define cimNativepciesupportDefault FALSE
-// Fusion Related
+// Fusion Related
#define cimAcDcMsgDefault FALSE
#define cimTimerTickTrackDefault FALSE
#define cimClockInterruptTagDefault FALSE
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 593bd6bfc7..0a339b02f7 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -39,8 +39,8 @@ static void enable_rom(void)
pci_io_write_config32(dev, 0x44, dword);
/* SB800 LPC Bridge 0:20:3:48h.
- * BIT0: Port Enable for SuperIO 0x2E-0x2F
- * BIT1: Port Enable for SuperIO 0x4E-0x4F
+ * BIT0: Port Enable for SuperIO 0x2E-0x2F
+ * BIT1: Port Enable for SuperIO 0x4E-0x4F
* BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
* BIT6: Port Enable for RTC IO 0x70-0x73
* BIT21: Port Enable for Port 0x80
diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h
index cfb983c2cf..cfb983c2cf 100755..100644
--- a/src/southbridge/amd/cimx/sb900/Amd.h
+++ b/src/southbridge/amd/cimx/sb900/Amd.h
diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
index a86f24b6fb..a86f24b6fb 100755..100644
--- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h
+++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h
index 5e2b05cfdc..5e2b05cfdc 100755..100644
--- a/src/southbridge/amd/cimx/sb900/SbEarly.h
+++ b/src/southbridge/amd/cimx/sb900/SbEarly.h
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 3fb45dea64..3fb45dea64 100755..100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e04cec0e04..e84743bc20 100755..100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -73,8 +73,8 @@ static void sb900_enable_rom(void)
pci_io_write_config32(dev, 0x44, dword);
/* SB900 LPC Bridge 0:20:3:48h.
- * BIT0: Port Enable for SuperIO 0x2E-0x2F
- * BIT1: Port Enable for SuperIO 0x4E-0x4F
+ * BIT0: Port Enable for SuperIO 0x2E-0x2F
+ * BIT1: Port Enable for SuperIO 0x4E-0x4F
* BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
* BIT6: Port Enable for RTC IO 0x70-0x73
* BIT21: Port Enable for Port 0x80
@@ -86,7 +86,7 @@ static void sb900_enable_rom(void)
/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
/* Set the 4MB enable bits */
word = pci_io_read_config16(dev, 0x6c);
- word = 0xFFC0;
+ word = 0xFFC0;
pci_io_write_config16(dev, 0x6c, word);
}
diff --git a/src/southbridge/amd/cimx/sb900/cbtypes.h b/src/southbridge/amd/cimx/sb900/cbtypes.h
index 4c97a33ed6..4c97a33ed6 100755..100644
--- a/src/southbridge/amd/cimx/sb900/cbtypes.h
+++ b/src/southbridge/amd/cimx/sb900/cbtypes.h
diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h
index 96afc42736..96afc42736 100755..100644
--- a/src/southbridge/amd/cimx/sb900/chip.h
+++ b/src/southbridge/amd/cimx/sb900/chip.h
diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c
index dd875dcfd6..dd875dcfd6 100755..100644
--- a/src/southbridge/amd/cimx/sb900/chip_name.c
+++ b/src/southbridge/amd/cimx/sb900/chip_name.c
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index bd4fd4fa22..1176ca598c 100755..100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -142,7 +142,7 @@ void sb_Late_Post(void)
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbLatePost(&sb_early_cfg);
-
+
//Set ACPI SCI IRQ to 0x9.
data = CONFIG_ACPI_SCI_IRQ;
outb(0x10, 0xC00);
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 71c65e31c6..71c65e31c6 100755..100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index 48bfe36556..48bfe36556 100755..100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h
index f4d1493fba..f4d1493fba 100755..100644
--- a/src/southbridge/amd/cimx/sb900/lpc.h
+++ b/src/southbridge/amd/cimx/sb900/lpc.h
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
index 1fbf5ac6c7..1fbf5ac6c7 100755..100644
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h
index e6ade1ed48..e6ade1ed48 100755..100644
--- a/src/southbridge/amd/cimx/sb900/smbus.h
+++ b/src/southbridge/amd/cimx/sb900/smbus.h