SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper

Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/561
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

18 files changed, 1894 insertions, 2 deletions

diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig
index 8f12b90b57..f61b75a7b2 100644
--- a/src/southbridge/amd/cimx/Kconfig
+++ b/src/southbridge/amd/cimx/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -21,5 +21,6 @@ config AMD_SB_CIMX
 	bool
 	default n
 
+source src/southbridge/amd/cimx/sb700/Kconfig
 source src/southbridge/amd/cimx/sb800/Kconfig
 source src/southbridge/amd/cimx/sb900/Kconfig
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
index 421a11c99d..80c6378c0d 100644
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -16,5 +16,6 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h
new file mode 100644
index 0000000000..fbd5531fdd
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Amd.h
@@ -0,0 +1,363 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+// AGESA Types and Definitions
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define LAST_ENTRY 0xFFFFFFFF
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+#define IN
+#define OUT
+
+#ifndef Int16FromChar
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#endif
+#ifndef Int32FromChar
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+#endif
+
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+
+typedef unsigned int AGESA_STATUS;
+
+#define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)
+#define AGESA_ALERT         ((AGESA_STATUS) 0x40000000)
+#define AGESA_WARNING       ((AGESA_STATUS) 0x40000001)
+#define AGESA_UNSUPPORTED   ((AGESA_STATUS) 0x80000003)
+#define AGESA_ERROR         ((AGESA_STATUS) 0xC0000001)
+#define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
+#define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
+
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+	PreMemHeap = 0,                                           ///< Create heap in cache.
+	PostMemDram,                                              ///< Create heap in memory.
+	ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+	AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+	AccessWidth16,                                            ///< Access width is 16 bits.
+	AccessWidth32,                                            ///< Access width is 32 bits.
+	AccessWidth64,                                            ///< Access width is 64 bits.
+
+	AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+	AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+	AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+	AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+typedef struct _AMD_CONFIG_PARAMS {
+	IN       unsigned int          ImageBasePtr;     ///< The AGESA Image base address.
+	IN       unsigned int          Func;             ///< The service desired, @sa dispatch.h.
+	IN       unsigned int          AltImageBasePtr;  ///< Alternate Image location
+	IN       unsigned int          PcieBasePtr;      ///< PCIe MMIO Base address, if configured.
+	union {                                    ///< Callback pointer
+		IN       unsigned long long          PlaceHolder;    ///< Place holder
+		IN       CALLOUT_ENTRY   CalloutPtr;     ///< For Callout from AGESA
+	} CALLBACK;
+	IN OUT   unsigned int          Reserved[2];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// AGESA Binary module header structure
+typedef struct _AMD_IMAGE_HEADER {
+	IN       unsigned int  Signature;                          ///< Binary Signature
+	IN       signed char   CreatorID[8];                       ///< 8 characters ID
+	IN       signed char   Version[12];                        ///< 12 characters version
+	IN       unsigned int  ModuleInfoOffset;                   ///< Offset of module
+	IN       unsigned int  EntryPointAddress;                  ///< Entry address
+	IN       unsigned int  ImageBase;                          ///< Image base
+	IN       unsigned int  RelocTableOffset;                   ///< Relocate Table offset
+	IN       unsigned int  ImageSize;                          ///< Size
+	IN       unsigned short  Checksum;                           ///< Checksum
+	IN       unsigned char   ImageType;                          ///< Type
+	IN       unsigned char   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+	IN       unsigned int          ModuleHeaderSignature;      ///< Module signature
+	IN       signed char           ModuleIdentifier[8];        ///< 8 characters ID
+	IN       signed char           ModuleVersion[12];          ///< 12 characters version
+	IN       MODULE_ENTRY    ModuleDispatcherPtr;        ///< A pointer point to dispatcher
+	IN       struct _AMD_MODULE_HEADER  *NextBlockPtr;    ///< Next module header link
+} AMD_MODULE_HEADER;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function (3-bits)
+//   11:00   Offset  (12-bits)
+
+#if 0
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
+		(((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
+#endif
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct _SB_CPUID_DATA {
+	IN OUT   unsigned int          EAX_Reg;                ///< CPUID instruction result in EAX
+	IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
+	IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
+	IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
+} SB_CPUID_DATA;
+
+#define WARM_RESET 1
+#define COLD_RESET 2      // Cold reset
+#define RESET_CPU  4      // Triggers a CPU reset
+
+/// HT frequency for external callbacks
+typedef enum {
+	HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+	HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+	HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+	HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+	HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+	HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+	HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+	HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+	HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+	HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+	HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+	HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+	HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+	HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+	HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+	HT_FREQUENCY_3200M         = 19                 ///< HT speed 3200 for external callbacks
+} HT_FREQUENCIES;
+
+#ifndef BIT0
+#define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+#define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+#define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+#define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+#define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+#define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+#define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+#define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+#define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+#define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+#define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+#define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+#define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+#define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+#define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+#define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+#define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+#define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+#define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+#define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+#define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+#define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+#define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+#define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+#define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+#define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+#define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+#define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+#define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+#define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+#define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+#define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+#define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+#define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+#define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+#define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+#define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+#define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+#define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+#define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+#define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+#define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+#define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+#define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+#define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+#define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+#define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+#define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+#define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+#define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+#define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+#define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+#define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+#define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+#define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+#define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+#define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+#define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+#define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+#define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+#define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+#define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+#define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+#define BIT63       0x8000000000000000ull
+#endif
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h
new file mode 100644
index 0000000000..dbf43ca658
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_SB_LIB_H_
+#define _AMD_SB_LIB_H_
+
+typedef signed char  *va_list;
+#ifndef _INTSIZEOF
+  #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+  #define va_start(ap, v)  ( ap = (va_list)&(v) + _INTSIZEOF (v) )
+#endif
+#define va_arg(ap, t)    ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
+#define va_end(ap)      ( ap = (va_list)0 )
+
+
+#pragma pack (push, 1)
+
+#define IMAGE_ALIGN          32*1024
+#define NUM_IMAGE_LOCATION   32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
+
+//Hook Call
+
+typedef struct _CIMFILEHEADER
+{
+	unsigned int  AMDLogo;
+	unsigned long long  CreatorID;
+	unsigned int  Version1;
+	unsigned int  Version2;
+	unsigned int  Version3;
+	unsigned int  ModuleInfoOffset;
+	unsigned int  EntryPoint;
+	unsigned int  ImageBase;
+	unsigned int  RelocTableOffset;
+	unsigned int  ImageSize;
+	unsigned short  CheckSum;
+	unsigned char ImageType;
+	unsigned char Reserved2;
+} CIMFILEHEADER;
+
+#pragma pack (pop)
+
+typedef enum
+{
+	AccWidthUint8 = 0,
+	AccWidthUint16,
+	AccWidthUint32,
+} ACC_WIDTH;
+
+#define S3_SAVE  0x80
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS  AmdSbDispatcher (IN void *pConfig);
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
new file mode 100644
index 0000000000..27338fc63d
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Kconfig
@@ -0,0 +1,63 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_CIMX_SB700
+	bool
+	select IOAPIC
+	select AMD_SB_CIMX
+
+if SOUTHBRIDGE_AMD_CIMX_SB700
+config SATA_CONTROLLER_MODE
+	hex
+	default 0x0
+	help
+		0x0 = Native IDE mode.
+		0x1 = RAID mode.
+		0x2 = AHCI mode.
+		0x3 = Legacy IDE mode.
+		0x4 = IDE->AHCI mode.
+		0x5 = AHCI mode as 7804 ID (AMD driver).
+		0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
+
+config PCIB_ENABLE
+	bool
+	default n
+	help
+		n = Disable PCI Bridge Device 14 Function 4.
+		y = Enable PCI Bridge Device 14 Function 4.
+
+config ACPI_SCI_IRQ
+	hex
+	default 0x9
+	help
+		Set SCI IRQ to 9.
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/cimx/sb700/bootblock.c"
+
+config REDIRECT_SBCIMX_TRACE_TO_SERIAL
+	bool "Redirect AMD Southbridge CIMX Trace to serial console"
+	default n
+	help
+	  This Option allows you to redirect the AMD Southbridge CIMX Trace
+	  debug information to the serial console.
+
+	  Warning: Only enable this option when debuging or tracing AMD CIMX code.
+endif #SOUTHBRIDGE_AMD_CIMX_SB700
+
diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc
new file mode 100644
index 0000000000..7929cf77c5
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Makefile.inc
@@ -0,0 +1,31 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+
+# SB700 Platform Files
+
+romstage-y += early.c
+romstage-y += smbus.c
+
+ramstage-y += late.c
+
+driver-y   += smbus.c
+driver-y   += lpc.c
+
+
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
new file mode 100644
index 0000000000..15e5b0702c
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_SB_CIMx_PLATFORM_H_
+#define _AMD_SB_CIMx_PLATFORM_H_
+
+#pragma pack(push,1)
+
+#include "cbtypes.h"
+#include <console/console.h>
+#include <console/loglevel.h>
+#ifdef NULL
+#undef NULL
+#endif
+#define NULL            0
+
+typedef struct _EXT_PCI_ADDR{
+	UINT32                  Reg :16;
+	UINT32                  Func:3;
+	UINT32                  Dev :5;
+	UINT32                  Bus :8;
+}EXT_PCI_ADDR;
+
+
+typedef union _PCI_ADDR{
+	UINT32                  ADDR;
+	EXT_PCI_ADDR            Addr;
+}PCI_ADDR;
+
+
+#ifdef CIM_DEBUG
+
+#if   CIM_DEBUG & 2
+void    TraceDebug( UINT32 Level, CHAR8 *Format, ...);
+#define TRACE(Arguments) TraceDebug Arguments
+#else
+#define TRACE(Arguments)
+#endif
+
+#if   CIM_DEBUG & 1
+void    TraceCode ( UINT32 Level, UINT32 Code);
+#define TRACECODE(Arguments) TraceCode Arguments
+#else
+#define TRACECODE(Arguments)
+#endif
+#else
+	#if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
+		#define TRACE(Arguments) printk Arguments
+	#else
+		#define TRACE(Arguments) do {} while(0)
+	#endif
+	#define TRACECODE(Arguments)
+#endif
+
+#define FIXUP_PTR(ptr)  ptr
+
+#pragma pack(pop)
+
+#include "OEM.h"
+#include "Amd.h"
+#include "ACPILIB.h"
+#include "SBTYPE.h"
+#include "sbAMDLIB.h"
+#include "SBCMNLIB.h"
+#include "SB700.h"
+#include "SBDEF.h"
+
+#define DMSG_SB_TRACE   0x02
+
+#endif  //#ifndef _AMD_SB_CIMx_PLATFORM_H_
+
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
new file mode 100644
index 0000000000..401c039165
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+
+#if CONFIG_CONSOLE_POST == 1
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#ifndef CONFIG_TTYS0_DIV
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+#define CONFIG_TTYS0_DIV	(115200/CONFIG_TTYS0_BAUD)
+#endif // CONFIG_TTYS0_DIV
+
+#define UART_LCS	CONFIG_TTYS0_LCS
+
+#endif // CONFIG_CONSOLE_POST == 1
+
+
+static void sb700_enable_rom(void)
+{
+	u32 word;
+	u32 dword;
+	device_t dev;
+
+	dev = PCI_DEV(0, 0x14, 0x03);
+	/* SB700 LPC Bridge 0:20:3:44h.
+	 * BIT6: Port Enable for serial port 0x3f8-0x3ff
+	 * BIT29: Port Enable for KBC port 0x60 and 0x64
+	 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+	 */
+	dword = pci_io_read_config32(dev, 0x44);
+	//dword |= (1<<6) | (1<<29) | (1<<30) ;
+	/*Turn on all of LPC IO Port decode enable */
+	dword = 0xffffffff;
+	pci_io_write_config32(dev, 0x44, dword);
+
+	/* SB700 LPC Bridge 0:20:3:48h.
+	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
+	 * BIT1: Port Enable for SuperIO 0x4E-0x4F
+	 * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+	 * BIT6: Port Enable for RTC IO 0x70-0x73
+	 * BIT21: Port Enable for Port 0x80
+	 */
+	dword = pci_io_read_config32(dev, 0x48);
+	dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+	pci_io_write_config32(dev, 0x48, dword);
+
+	/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+	/* Set the 4MB enable bits */
+	word = pci_io_read_config16(dev, 0x6c);
+	word = 0xFFC0;
+	pci_io_write_config16(dev, 0x6c, word);
+}
+
+static void bootblock_southbridge_init(void)
+{
+	/* Setup the rom access for 2M */
+	sb700_enable_rom();
+}
diff --git a/src/southbridge/amd/cimx/sb700/cbtypes.h b/src/southbridge/amd/cimx/sb700/cbtypes.h
new file mode 100644
index 0000000000..d37e1e3402
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/cbtypes.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _CBTYPES_H_
+#define _CBTYPES_H_
+
+//#include <stdint.h>
+
+typedef signed long long __int64;
+typedef void VOID;
+typedef unsigned int UINTN;
+typedef signed char CHAR8;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned long long UINT64;
+
+#ifndef TRUE
+#define TRUE  1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+typedef unsigned char BOOLEAN;
+
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+
+#ifndef IN
+#define IN
+#endif
+#ifndef OUT
+#define OUT
+#endif
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h
new file mode 100644
index 0000000000..ef294f450c
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/chip.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _CIMX_SB700_CHIP_H_
+#define _CIMX_SB700_CHIP_H_
+
+extern struct chip_operations southbridge_amd_cimx_sb700_ops;
+
+/*
+ * configuration set in mainboard/devicetree.cb
+ *  boot_switch_sata_ide:
+ *   0 -set SATA as primary, PATA(IDE) as secondary.
+ *   1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
+ *  gpp_configuration - The configuration of General Purpose Port A/B/C/D
+ *   0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
+ *   2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
+ *   3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ *   4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+struct southbridge_amd_cimx_sb700_config
+{
+	u32 boot_switch_sata_ide : 1;
+	u8  gpp_configuration;
+};
+
+#endif /* _CIMX_SB700_CHIP_H_ */
diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c
new file mode 100644
index 0000000000..13d2276641
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/chip_name.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations southbridge_amd_cimx_sb700_ops = {
+	CHIP_NAME("AMD South Bridge  SB700")
+};
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
new file mode 100644
index 0000000000..c899320c48
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+//#include <config.h>
+#include <stdint.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>            /* inl, outl */
+#include <arch/romcc_io.h>      /* device_t */
+#include "Platform.h"
+#include "sb_cimx.h"
+#include "sb700_cfg.h"                /*sb700_cimx_config*/
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "smbus.h"
+
+
+#if CONFIG_RAMINIT_SYSINFO == 1
+/**
+ * @brief Get SouthBridge device number
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus)
+{
+	device_t dev;
+
+	printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__);
+	dev = pci_locate_device_on_bus(
+			PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM),
+			bus);
+
+	printk(BIOS_SPEW, "SB700 - Early.c - %s - End.\n", __func__);
+	return (dev >> 15) & 0x1f;
+}
+#endif
+
+/**
+ * @brief Enable A-Link Express Configuration DMA Access.
+ */
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ *        wrapper of sbPowerOnInit entry point.
+ */
+void sb_Poweron_Init(void)
+{
+	AMDSBCFG sb_early_cfg;
+
+	printk(BIOS_SPEW, "cimx/sb700 early.c, %s() Start:\n", __func__);
+	/* Enable A-Link Base Address */
+	//sb_enable_alink ();
+
+	sb700_cimx_config(&sb_early_cfg);
+	sbPowerOnInit(&sb_early_cfg);
+	printk(BIOS_SPEW, "cimx/sb700 early.c, %s() End\n", __func__);
+}
+
+void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
+{
+	/* TODO: Now assume wio_index=0 */
+	device_t dev;
+	u8 reg8;
+
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
+	dev = PCI_DEV(0, 0x14, 3);	/* LPC Controller */
+	pci_write_config32(dev, 0x64, base);
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 |= 1 << 2;
+	pci_write_config8(dev, 0x48, reg8);
+}
+
+void sb7xx_51xx_disable_wideio(u8 wio_index)
+{
+	/* TODO: Now assume wio_index=0 */
+	device_t dev;
+	u8 reg8;
+
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
+	dev = PCI_DEV(0, 0x14, 3);	/* LPC Controller */
+	pci_write_config32(dev, 0x64, 0);
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(dev, 0x48, reg8);
+}
+
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
new file mode 100644
index 0000000000..4e51e0a3e3
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -0,0 +1,319 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <device/device.h>      /* device_t */
+#include <device/pci.h>         /* device_operations */
+#include <device/pci_ids.h>
+#include <arch/ioapic.h>
+#include <device/smbus.h>       /* smbus_bus_operations */
+#include <console/console.h>    /* printk */
+#include "lpc.h"                /* lpc_read_resources */
+#include "Platform.h"   /* Platfrom Specific Definitions */
+#include "sb_cimx.h"
+#include "sb700_cfg.h"                /* sb700 Cimx configuration */
+#include "chip.h"               /* struct southbridge_amd_cimx_sb700_config */
+
+
+/*implement in mainboard.c*/
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config
+static AMDSBCFG *sb_config = &sb_late_cfg;
+
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func      Southbridge CIMx Function ID.
+ * @param[in] data      Southbridge Input Data.
+ * @param[in] sb_config Southbridge configuration structure pointer.
+ *
+ */
+u32 sb700_callout_entry(u32 func, u32 data, void* config)
+{
+	u32 ret = 0;
+
+	printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n");
+	printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n");
+	return ret;
+}
+
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static void lpc_enable_resources(device_t dev)
+{
+
+	printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__);
+	pci_dev_enable_resources(dev);
+	lpc_enable_childrens_resources(dev);
+	printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__);
+}
+
+static struct device_operations lpc_ops = {
+	.read_resources = lpc_read_resources,
+	.set_resources = lpc_set_resources,
+	.enable_resources = lpc_enable_resources,
+	.init = 0,
+	.scan_bus = scan_static_bus,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_LPC,
+};
+
+
+static struct device_operations sata_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390
+};
+
+#if CONFIG_USBDEBUG
+static void usb_set_resources(struct device *dev)
+{
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__);
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+
+	pci_dev_set_resources(dev);
+
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+	printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__);
+}
+#endif
+
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+#if CONFIG_USBDEBUG
+	.set_resources = usb_set_resources,
+#else
+	.set_resources = pci_dev_set_resources,
+#endif
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+/*
+ * The pci id of usb ctrl 0 and 1 are the same.
+ */
+static const struct pci_driver usb_ohci123_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
+};
+
+static const struct pci_driver usb_ohci3_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_1,
+};
+
+static const struct pci_driver usb_ehci123_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
+};
+
+static const struct pci_driver usb_ohci4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */
+};
+
+static struct device_operations azalia_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver azalia_driver __pci_driver = {
+	.ops = &azalia_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_HDA,
+};
+
+
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = 0,
+	.scan_bus = pci_scan_bridge,
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_PCI,
+};
+
+
+static void sb700_enable(device_t dev)
+{
+	struct southbridge_amd_cimx_sb700_config *sb_chip =
+		(struct southbridge_amd_cimx_sb700_config *)(dev->chip_info);
+
+	printk(BIOS_DEBUG, "sb700_enable() ");
+	switch (dev->path.pci.devfn) {
+		case (0x11 << 3) | 0: /* 0:11.0  SATA */
+			sb700_cimx_config(sb_config);
+			if (dev->enabled) {
+				sb_config->SataController = CIMX_OPTION_ENABLED;
+				if (1 == sb_chip->boot_switch_sata_ide)
+					sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
+				else if (0 == sb_chip->boot_switch_sata_ide)
+					sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
+			} else {
+				sb_config->SataController = CIMX_OPTION_DISABLED;
+			}
+			break;
+
+		case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
+		case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
+		case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
+		case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
+			break;
+
+		case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+			{
+#if 1
+				u32 ioapic_base;
+				printk(BIOS_DEBUG, "sm_init().\n");
+				ioapic_base = IO_APIC_ADDR;
+				clear_ioapic(ioapic_base);
+				/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
+				/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+				setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+#elif (CONFIG_APIC_ID_OFFSET > 0)
+				/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+				setup_ioapic(ioapic_base, 0);
+#else
+#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
+#endif
+#endif
+			}
+			break;
+
+		case (0x14 << 3) | 1: /* 0:14:1 IDE */
+			break;
+
+		case (0x14 << 3) | 2: /* 0:14:2 HDA */
+			if (dev->enabled) {
+				if (AZALIA_DISABLE == sb_config->AzaliaController) {
+					sb_config->AzaliaController = AZALIA_AUTO;
+				}
+				printk(BIOS_DEBUG, "hda enabled\n");
+			} else {
+				sb_config->AzaliaController = AZALIA_DISABLE;
+				printk(BIOS_DEBUG, "hda disabled\n");
+			}
+			break;
+
+
+		case (0x14 << 3) | 3: /* 0:14:3 LPC */
+			break;
+
+		case (0x14 << 3) | 4: /* 0:14:4 PCI */
+			break;
+
+		case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+			/* call CIMX entry after last device enable */
+			sb_Before_Pci_Init();
+			break;
+
+		default:
+			break;
+	}
+}
+
+struct chip_operations southbridge_amd_cimx_sb700_ops = {
+	CHIP_NAME("ATI SB700")
+	.enable_dev = sb700_enable,
+};
+
+/**
+ * @brief SB Cimx entry point sbBeforePciInit wrapper
+ */
+void sb_Before_Pci_Init(void)
+{
+	printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
+	/* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
+	//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+	//AmdSbDispatcher(sb_config);
+	sbBeforePciInit(sb_config);
+	printk(BIOS_SPEW, "sb700 %s End\n", __func__);
+}
+
+void sb_After_Pci_Init(void)
+{
+	printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
+	/* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
+	//sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
+	//AmdSbDispatcher(sb_config);
+	sbAfterPciInit(sb_config);
+	printk(BIOS_SPEW, "sb700 %s End\n", __func__);
+}
+
+void sb_Late_Post(void)
+{
+	printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
+	/* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
+	//sb_config->StdHeader.Func = SB_LATE_POST_INIT;
+	//AmdSbDispatcher(sb_config);
+	sbLatePost(sb_config);
+	printk(BIOS_SPEW, "sb700 %s End\n", __func__);
+}
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
new file mode 100644
index 0000000000..e43193a9c5
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/pci.h>
+#include "lpc.h"
+#include <bitops.h>
+#include <arch/io.h>
+#include <console/console.h>	/* printk */
+#include <cbmem.h>
+
+#define BIOSRAM_INDEX   0xcd4
+#define BIOSRAM_DATA    0xcd5
+
+void set_cbmem_toc(struct cbmem_entry *toc)
+{
+	u32 dword = (u32) toc;
+	int nvram_pos = 0xfc, i;
+	for (i = 0; i<4; i++) {
+		outb(nvram_pos, BIOSRAM_INDEX);
+		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+		nvram_pos++;
+	}
+}
+
+void lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	compact_resources(dev);
+	printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
+}
+
+void lpc_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
+	pci_dev_set_resources(dev);
+
+	/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+	res = find_resource(dev, SPIROM_BASE_ADDRESS);
+	pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
+	printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ */
+void lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	u32 reg, reg_x;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = dev->link_list; link; link = link->next) {
+		device_t child;
+		for (child = link->children; child;
+		     child = child->sibling) {
+			if (child->enabled
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for (res = child->resource_list; res; res = res->next) {
+					u32 base, end;	/*  don't need long long */
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+/*
+					printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+*/
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	/* Set WideIO for as many IOs found (fall through is on purpose) */
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
+		break;
+	}
+	printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
+}
diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h
new file mode 100644
index 0000000000..edb13f8576
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/lpc.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SB700_LPC_H_
+#define _SB700_LPC_H_
+
+
+#define SPIROM_BASE_ADDRESS	0xA0 /* SPI ROM base address */
+
+void lpc_read_resources(device_t dev);
+void lpc_set_resources(device_t dev);
+void lpc_enable_childrens_resources(device_t dev);
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h
new file mode 100644
index 0000000000..632e4cdcd5
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _CIMX_H_
+#define _CIMX_H_
+
+#define PM_INDEX	0xcd6
+#define PM_DATA		0xcd7
+
+#define REV_SB700_A11	0x11
+#define REV_SB700_A12	0x12
+
+
+/**
+ * AMD South Bridge CIMx entry point wrapper
+ */
+void sb_Poweron_Init(void);
+void sb_Before_Pci_Init(void);
+void sb_After_Pci_Init(void);
+void sb_Mid_Post_Init(void);
+void sb_Late_Post(void);
+
+void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
+void sb7xx_51xx_disable_wideio(u8 wio_index);
+
+#if CONFIG_RAMINIT_SYSINFO == 1
+/**
+ * @brief Get SouthBridge device number, called by finalize_node_setup()
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus);
+#endif
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c
new file mode 100644
index 0000000000..e155aca800
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/smbus.c
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include "smbus.h"
+#include <console/console.h>	/* printk */
+
+static inline void smbus_delay(void)
+{
+	outb(inb(0x80), 0x80);
+}
+
+static int smbus_wait_until_ready(u32 smbus_io_base)
+{
+	u32 loops;
+
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;
+		if (val == 0) {	/* ready now */
+			return 0;
+		}
+		outb(val, smbus_io_base + SMBHSTSTAT);
+	} while (--loops);
+
+	return -2;		/* time out */
+}
+
+static int smbus_wait_until_done(u32 smbus_io_base)
+{
+	u32 loops;
+
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;	/* mask off reserved bits */
+		if (val & 0x1c) {
+			return -5;	/* error */
+		}
+		if (val == 0x02) {
+			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
+			return 0;
+		}
+	} while (--loops);
+
+	return -3;		/* timeout */
+}
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n");
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTCMD);
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n");
+	return byte;
+}
+
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n");
+	/* set the command... */
+	outb(val, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n");
+	return 0;
+}
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n");
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n");
+	return byte;
+}
+
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n");
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	/* output value */
+	outb(val, smbus_io_base + SMBHSTDAT0);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n");
+	return 0;
+}
+
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n");
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n");
+}
+
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n");
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n");
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n");
+	/* read axindc to tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	tmp = inl(AB_DATA);
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* write tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n");
+}
+
diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h
new file mode 100644
index 0000000000..10e08742a7
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/smbus.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SB700_SMBUS_H_
+#define _SB700_SMBUS_H_
+
+//#include <stdint.h>
+#include <Platform.h> /* SMBUS0_BASE_ADDRESS */
+#ifndef SMBUS0_BASE_ADDRESS
+#error SMBUS0_BASE_ADDRESS not define
+#endif
+#define SMBUS_IO_BASE	SMBUS0_BASE_ADDRESS
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+/*//SB00.H
+#define AX_INDXC  0
+#define AX_INDXP  2
+#define AXCFG     4
+#define ABCFG     6
+#define RC_INDXC  1
+#define RC_INDXP  3
+*/
+
+#define AB_INDX   0xCD8
+#define AB_DATA   (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)		\
+	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
+#define rcindxc_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
+#define rcindxp_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
+
+#endif //_SB700_SMBUS_H_