diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2014-07-22 23:12:38 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-24 12:43:03 +0200 |
| commit | 65fa598d2aba9d688d7506cdcaceb393d53e892b (patch) | |
| tree | 9158808f5ac40040bfae101ed5791d92aad52da4 /src/southbridge/amd/cimx | |
| parent | aedcc10ad30f3fcc1397035876672d235418393f (diff) | |
southbridge/amd: Remove trailing whitespace
Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6334
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/cimx')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/SbPlatform.h | 76 |
2 files changed, 42 insertions, 42 deletions
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index ea3f71958a..b26d429bd3 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -21,8 +21,8 @@ * */ -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> @@ -162,7 +162,7 @@ typedef union _PCI_ADDR { #include <spi-generic.h> #endif -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 176ad87eb4..6371bcd69e 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -21,8 +21,8 @@ * */ -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> @@ -107,48 +107,48 @@ typedef union _PCI_ADDR { * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable */ -#define SB_CIMx_PARAMETER 0x02 +#define SB_CIMx_PARAMETER 0x02 // Generic -#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumDefault TRUE #define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x00 // Disable -#define cimSpiFastReadSpeedDefault 0x00 // NULL +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x00 // Disable +#define cimSpiFastReadSpeedDefault 0x00 // NULL // GPP/AB Controller -#define cimNbSbGen2Default TRUE -#define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE +#define cimNbSbGen2Default TRUE +#define cimAlinkPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE // USB Controller -#define cimUsbPhyPowerDownDefault FALSE +#define cimUsbPhyPowerDownDefault FALSE // GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 // Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable +#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE // Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE #endif // _AMD_SBPLATFORM_H_ |