diff options
| author | Martin Roth <martin@se-eng.com> | 2012-12-05 15:50:32 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-12-12 22:34:32 +0100 |
| commit | 3aef7b4f63b3870e3699d5408d0fb8917c5eb135 (patch) | |
| tree | b89512d8cdbb67cd9dd5050377163662294b9560 /src/southbridge/amd/cimx | |
| parent | 3316cf2ff80f379b609115f375f73ef4b9e7d8f4 (diff) | |
Fix SPI BAR special case in lpc_set_resources
There was already a special case for the SPI base address in
lpc_set_resources for southbridge/amd/cimx/sb800 and
southbridge/amd/agesa/hudson, but it needed to be modified
to keep from killing the IMC rom during initialization. As
soon as the BAR is disabled by setting the new base address,
the IMC dies. The fix is to make sure it's still enabled
when setting the new base address instead of setting the new
address then re-enabling it.
Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER
to more accurately describe what we're using.
Change-Id: I216d75b722c4332c239d487111a9880eabf59e91
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1975
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/lpc.c | 11 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/lpc.h | 2 |
2 files changed, 8 insertions, 5 deletions
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index caac5b14d2..44dd07dd83 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/pci.h> +#include <device/pci_def.h> #include <arch/ioapic.h> #include "lpc.h" #include <arch/io.h> @@ -32,7 +33,7 @@ void lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + pci_get_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); /* SPI ROM base address */ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -61,11 +62,13 @@ void lpc_set_resources(struct device *dev) struct resource *res; printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); + + /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); + res->base |= PCI_COMMAND_MEMORY; + pci_dev_set_resources(dev); - /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS); - pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 3d6a17a381..3fc8d39a10 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -20,7 +20,7 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ -#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); void lpc_set_resources(device_t dev); |