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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-15 20:07:53 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-05-18 06:48:57 +0200 |
commit | 61be3603f4b9f353e605d7b7c8d0d9f3b90f5636 (patch) | |
tree | 0de776853b482a83faff1ca5bbfdc2df243f7214 /src/southbridge/amd/cimx/sb900 | |
parent | 17bb225be7dd031b9803f33dec88e9d53e3a582f (diff) |
AGESA: Fix UMA calculations
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900')
-rw-r--r-- | src/southbridge/amd/cimx/sb900/Makefile.inc | 2 | ||||
-rw-r--r-- | src/southbridge/amd/cimx/sb900/ramtop.c | 43 |
2 files changed, 45 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index 05ebaead18..b09180cfa7 100644 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -20,11 +20,13 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c smbus_spd.c romstage-y += reset.c +romstage-y += ramtop.c ramstage-y += cfg.c ramstage-y += early.c ramstage-y += late.c ramstage-y += reset.c +ramstage-y += ramtop.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb900/ramtop.c b/src/southbridge/amd/cimx/sb900/ramtop.c new file mode 100644 index 0000000000..34e8364379 --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/ramtop.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <cbmem.h> +#include <southbridge/amd/cimx/cimx_util.h> + +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i < 4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); + nvram_pos++; + } +} + +unsigned long get_top_of_ram(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + for (xi = 0; xi < 4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} |