diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-02 12:30:06 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-07 18:09:06 +0200 |
| commit | 9344bde4fedfa7caed35aaa45d25c7184edcf4ae (patch) | |
| tree | 4099099a623d628b4419b57db9eeea101af2ef82 /src/southbridge/amd/cimx/sb900 | |
| parent | 7d87e767b612fc39bfe9cc7dbd1e714dbf6597cf (diff) | |
src/southbridge: Remove unnecessary whitespace
Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16852
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb900')
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/bootblock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 50d3087641..a06946352c 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -28,7 +28,7 @@ static void sb900_enable_rom(void) * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30) ; + //dword |= (1<<6) | (1<<29) | (1<<30); /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); @@ -41,7 +41,7 @@ static void sb900_enable_rom(void) * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); - dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21); pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ |