Addition of Family12/SB900 wrapper code

This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.

Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h
new file mode 100755
index 0000000000..f4d1493fba
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/lpc.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SB900_LPC_H_
+#define _SB900_LPC_H_
+
+
+#define SPIROM_BASE_ADDRESS	0xA0 /* SPI ROM base address */
+
+void lpc_read_resources(device_t dev);
+void lpc_set_resources(device_t dev);
+void lpc_enable_childrens_resources(device_t dev);
+
+#endif