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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-19 16:51:54 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-07-03 09:46:15 +0200 |
| commit | adf3d6ff52eb674267eacbf37f811c7144e857b3 (patch) | |
| tree | 72dea3e6d005e8f438951e431659dc96e7e03a93 /src/southbridge/amd/cimx/sb800 | |
| parent | 23b4f0c7344c199d5adb0aece8d3ca9a624f4a34 (diff) | |
AGESA: Clean separation of SPI flash
To be precise, wakeup from S3 does not involve SPI writing, while
preparing for it on cold power-ons currently does.
For S3DataTypeMtrr storage is changed such that the first 4 bytes
is the length of data stored like with the other two S3DataType.
Change-Id: Id920650474530d4191075da4ef70daa66c904c5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6085
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 2ed50967a9..5cf989fdd6 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -31,7 +31,7 @@ ramstage-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c |