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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-02-14 06:58:39 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-02-20 21:38:54 +0000
commitc0733e1639bc97cd1774c556edd6bb6526876529 (patch)
tree41bb4158f088aa89c05dc63fd3bdd6e9ae9fae4f /src/southbridge/amd/cimx/sb800
parentc92efa336397b917081706dabeb6f41cf69176e8 (diff)
ACPI: Use common OperationRegion for PCI_MMCONF
Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800')
-rw-r--r--src/southbridge/amd/cimx/sb800/acpi/pcie.asl4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
index 65ac920efa..f69ba1db24 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl
@@ -29,9 +29,7 @@ Scope(\) {
}
Scope(\_SB) {
- /* PCIe Configuration Space for 16 busses */
- OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
- Field(PCFG, ByteAcc, NoLock, Preserve) {
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
* The 8 comes from 8 functions per device, and 4096 bytes per function config space