diff options
| author | zbao <fishbaozi@gmail.com> | 2012-04-05 13:18:49 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-12 00:14:58 +0200 |
| commit | 9bcdbf8eaa0c73d130ba555163f89fa1759c8c99 (patch) | |
| tree | c8d480f7e75444037a5ba491ea3987282e2faa21 /src/southbridge/amd/cimx/sb800/lpc.h | |
| parent | 2c2e78d845cd28eb3b11c87fa3feafaf836cda7a (diff) | |
Add Southbridge support for S3.
1. Add some CIMX call for S3.
2. Detect sleep type.
Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/621
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/lpc.h')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/lpc.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 7b165f8d8e..3d6a17a381 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -20,7 +20,6 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ - #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); |