diff options
| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:03:44 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:08:57 +0200 |
| commit | feed329a0c006968242aa3065506b5f37f4308d4 (patch) | |
| tree | 0ef0e9e0c112230dd03fe14e199b0be74776b112 /src/southbridge/amd/cimx/sb800/lpc.c | |
| parent | 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f (diff) | |
AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/lpc.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/lpc.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 39762a9bec..bc643b5e3c 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> #include <device/pci.h> #include "lpc.h" @@ -25,6 +26,7 @@ void lpc_read_resources(device_t dev) { struct resource *res; + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n"); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ @@ -49,18 +51,20 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n"); } void lpc_set_resources(struct device *dev) { struct resource *res; + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); pci_dev_set_resources(dev); /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS); pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); - + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); } /** @@ -76,6 +80,7 @@ void lpc_enable_childrens_resources(device_t dev) int var_num = 0; u16 reg_var[3]; + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); @@ -170,4 +175,5 @@ void lpc_enable_childrens_resources(device_t dev) //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n"); } |