diff options
| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:03:44 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:08:57 +0200 |
| commit | feed329a0c006968242aa3065506b5f37f4308d4 (patch) | |
| tree | 0ef0e9e0c112230dd03fe14e199b0be74776b112 /src/southbridge/amd/cimx/sb800/cfg.c | |
| parent | 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f (diff) | |
AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/cfg.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/cfg.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 0a09e11e86..57ff7181af 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -31,8 +31,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) { if (!sb_config) { + printk(BIOS_DEBUG, "SB800 - Cfg.c - sb800_cimx_config - No sb_config.\n"); return; } + printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - Start.\n"); //memset(sb_config, 0, sizeof(AMDSBCFG)); /* header */ @@ -73,7 +75,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER; /* USB */ - sb_config->USBMODE.UsbModeReg = USB_CINFIG; + sb_config->USBMODE.UsbModeReg = USB_CONFIG; sb_config->SbUsbPll = 0; /* SATA */ @@ -99,25 +101,28 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->GppFunctionEnable = GPP_CONTROLLER; sb_config->GppLinkConfig = GPP_CFGMODE; //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; + sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; sb_config->GppUnhidePorts = TRUE; //visable always, even port empty - //sb_config->NbSbGen2 = TRUE; - //sb_config->GppGen2 = TRUE; + sb_config->NbSbGen2 = NB_SB_GEN2; + sb_config->GppGen2 = SB_GPP_GEN2; //cimx BTS fix sb_config->GppMemWrImprove = TRUE; sb_config->SbPcieOrderRule = TRUE; sb_config->AlinkPhyPllPowerDown = TRUE; sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving - sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong - sb_config->GecConfig = 0; //ENABLE GEC controller + sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06 + sb_config->GecConfig = GEC_CONFIG; #ifndef __PRE_RAM__ /* ramstage cimx config here */ if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; } - - //sb_config-> #endif //!__PRE_RAM__ + printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - End.\n"); } |