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| author | Stefan Reinauer <reinauer@chromium.org> | 2011-10-31 12:56:45 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-01 19:07:45 +0100 |
| commit | 5ff7c13e858a31addf1558731a12cf6c753b576d (patch) | |
| tree | 82ed6cf7b45f3a86c2c43ab87383355ed6012d6c /src/southbridge/amd/cimx/sb800/bootblock.c | |
| parent | 784544b934d67dc85ccfcf33e04ff148045836ad (diff) | |
remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/amd/cimx/sb800/bootblock.c')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 593bd6bfc7..0a339b02f7 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -39,8 +39,8 @@ static void enable_rom(void) pci_io_write_config32(dev, 0x44, dword); /* SB800 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) * BIT6: Port Enable for RTC IO 0x70-0x73 * BIT21: Port Enable for Port 0x80 |