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authorElyes HAOUAS <ehaouas@noos.fr>2016-10-02 12:30:06 +0200
committerMartin Roth <martinroth@google.com>2016-10-07 18:09:06 +0200
commit9344bde4fedfa7caed35aaa45d25c7184edcf4ae (patch)
tree4099099a623d628b4419b57db9eeea101af2ef82 /src/southbridge/amd/cimx/sb700
parent7d87e767b612fc39bfe9cc7dbd1e714dbf6597cf (diff)
src/southbridge: Remove unnecessary whitespace
Change-Id: Ibcac5dd60dc7da82bbeeb89ac445a5a1aa56ed3d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16852 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/cimx/sb700')
-rw-r--r--src/southbridge/amd/cimx/sb700/bootblock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 2f67a36106..e10bb05ca9 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -29,7 +29,7 @@ static void sb700_enable_rom(void)
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/
dword = pci_io_read_config32(dev, 0x44);
- //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ //dword |= (1<<6) | (1<<29) | (1<<30);
/*Turn on all of LPC IO Port decode enable */
dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword);
@@ -42,7 +42,7 @@ static void sb700_enable_rom(void)
* BIT21: Port Enable for Port 0x80
*/
dword = pci_io_read_config32(dev, 0x48);
- dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+ dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21);
pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */