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authorKevin Paul Herbert <kph@meraki.net>2014-12-24 18:43:20 -0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-15 08:50:22 +0100
commitbde6d309dfafe58732ec46314a2d4c08974b62d4 (patch)
tree17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/amd/cimx/sb700
parent4b10dec1a66122b515b2191f823d7fd379ec655f (diff)
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/amd/cimx/sb700')
-rw-r--r--src/southbridge/amd/cimx/sb700/late.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index b0ec2dcb2e..1e1357eba8 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -237,12 +237,12 @@ static void sb700_enable(device_t dev)
u32 ioapic_base;
printk(BIOS_DEBUG, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
- clear_ioapic(ioapic_base);
+ clear_ioapic((void *)ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
if (CONFIG_MAX_CPUS >= 16)
- setup_ioapic(ioapic_base, 0);
+ setup_ioapic((void *)ioapic_base, 0);
else
- setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
+ setup_ioapic((void *)ioapic_base, CONFIG_MAX_CPUS + 1);
}
break;