AMD/agesa: Add functions for AMD PCI IRQ routing

Port the changes that were made in amd/cimx to amd/agesa
as were done in:
   commit c93a75a5ab067f86104028b74d92fc54cb939cd5
   Author: Mike Loptien <mike.loptien@se-eng.com>
   Date:   Fri Jun 6 15:16:29 2014 -0600

      AMD/CIMx: Add functions for AMD PCI IRQ routing

This change also moves the PCI INT functions to
southbridge/amd so that they can be used by CIMX and
AGESA. The amd/persimmon board is updated for this
change.

Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
Reviewed-on: http://review.coreboot.org/6065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 0 insertions, 85 deletions

diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h
index 841325143f..a16091aabd 100644
--- a/src/southbridge/amd/cimx/cimx_util.h
+++ b/src/southbridge/amd/cimx/cimx_util.h
@@ -23,73 +23,6 @@
 
 #include <stdint.h>
 
-/*
- * PIRQ and device routing - these define the index
- * into the FCH PCI_INTR 0xC00/0xC01 interrupt
- * routing table
- */
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) || \
-	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900)
-#define FCH_INT_TABLE_SIZE 0x54
-#define PIRQ_NC		0x1F	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_E		0x04	/* INT E */
-#define PIRQ_F		0x05	/* INT F */
-#define PIRQ_G		0x06	/* INT G */
-#define PIRQ_H		0x07	/* INT H */
-#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
-#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
-#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
-#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
-#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTA */
-#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTA */
-#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTA */
-#define PIRQ_SCI	0x10	/* SCI IRQ */
-#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
-#define PIRQ_ASF	0x12	/* ASF */
-#define PIRQ_HDA	0x13	/* HDA		14h.2 */
-#define PIRQ_FC		0x14	/* FC */
-#define PIRQ_GEC	0x15	/* GEC */
-#define PIRQ_PMON	0x16	/* Performance Monitor */
-#define PIRQ_IMC0	0x20	/* IMC INT0 */
-#define PIRQ_IMC1	0x21	/* IMC INT1 */
-#define PIRQ_IMC2	0x22	/* IMC INT2 */
-#define PIRQ_IMC3	0x23	/* IMC INT3 */
-#define PIRQ_IMC4	0x24	/* IMC INT4 */
-#define PIRQ_IMC5	0x25	/* IMC INT5 */
-#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
-#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
-#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
-#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
-#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
-#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
-#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
-#define PIRQ_IDE	0x40	/* IDE		14h.1 */
-#define PIRQ_SATA	0x41	/* SATA		11h.0 */
-#define PIRQ_GPP0	0x50	/* GPP INT 0 */
-#define PIRQ_GPP1	0x51	/* GPP INT 1 */
-#define PIRQ_GPP2	0x52	/* GPP INT 2 */
-#define PIRQ_GPP3	0x53	/* GPP INT 3 */
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700)
-#define FCH_INT_TABLE_SIZE 0xD
-#define PIRQ_NC		0x1F	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_ACPI	0x04	/* ACPI */
-#define PIRQ_SMBUS	0x05	/* SMBUS */
-/* Index 6, 7, 8 are all reserved */
-#define PIRQ_E		0x09	/* INT E */
-#define PIRQ_F		0x0A	/* INT F */
-#define PIRQ_G		0x0B	/* INT G */
-#define PIRQ_H		0x0C	/* INT H */
-#endif
-
 /* FCH index/data registers */
 #define BIOSRAM_INDEX	0xcd4
 #define BIOSRAM_DATA	0xcd5
@@ -105,22 +38,4 @@ u8 pm_ioread(u8 reg);
 void pm2_iowrite(u8 reg, u8 value);
 u8 pm2_ioread(u8 reg);
 
-#ifndef __PRE_RAM__
-
-struct pirq_struct {
-u8 devfn;
-u8 PIN[4];	/* PINA/B/C/D are index 0/1/2/3 */
-};
-
-extern const struct pirq_struct * pirq_data_ptr;
-extern u32 pirq_data_size;
-extern const u8 * intr_data_ptr;
-extern const u8 * picr_data_ptr;
-
-u8 read_pci_int_idx(u8 index, int mode);
-void write_pci_int_idx(u8 index, int mode, u8 data);
-void write_pci_cfg_irqs(void);
-void write_pci_int_table (void);
-#endif /* __PRE_RAM */
-
 #endif /* CIMX_UTIL_H */