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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2017-03-08 17:38:27 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-03-09 17:22:25 +0100 |
| commit | eaee1d8a5f6a5a70f7bdf10825e047c0529d5157 (patch) | |
| tree | f4788f667b1da1c3df979768871695e3b6fdeb42 /src/southbridge/amd/amd8132 | |
| parent | 18cb7e66bd52d68e59191d0d98236973213e6515 (diff) | |
google/pyro: Update DPTF settings
1. Update DPTF TSR1 passive trigger points.
TSR1 passive point: 50
2. Update DPTF PL1 Minimum
PL1 min: 2.5W
BUG=b:35586881
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ia2634f40098d026c4d228fab4b7c05501c1ff05f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/amd/amd8132')
0 files changed, 0 insertions, 0 deletions