diff options
| author | Julius Werner <jwerner@chromium.org> | 2016-10-03 12:52:55 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-10-07 17:55:47 +0200 |
| commit | 93b51e7ac9242738a9e3354661ea7a9980938e0a (patch) | |
| tree | fe0274956f49ba5ad65fe13a2b01e4abea6eee0f /src/southbridge/amd/amd8131 | |
| parent | e06a1b895c9905c53faaacf9286bafea7a3ef921 (diff) | |
ec/google/chromeec: Add minimum delay between SPI CS assertions
Some Chrome OS ECs require a small amount of time after a SPI
transaction to reset their controllers before they can service the next
CS assertion. The kernel and depthcharge have always enforced a 200us
minimum delay for this... coreboot should've done the same.
BRANCH=gru
BUG=chrome-os-partner:58046
TEST=Booted Kevin in recovery mode, confirmed that recovery events got
logged with correct timestamps in eventlog.
Change-Id: I32ec343f3293ac93729d3e6e2f43d7605a396cdb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b9e4696533d4318ae7c8715b71ab963d8897c16c
Original-Change-Id: I6a7baf7859d5d50e299495d118e7890dcaa2c1b0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/392206
Original-Tested-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: https://review.coreboot.org/16885
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd/amd8131')
0 files changed, 0 insertions, 0 deletions