diff options
| author | Eric Biederman <ebiederm@xmission.com> | 2004-10-21 10:44:08 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2004-10-21 10:44:08 +0000 |
| commit | dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d (patch) | |
| tree | e813d3f9dea80d35cbc29d6bf35995fec0a06ab9 /src/southbridge/amd/amd8131 | |
| parent | f3aa4707d3bef9f529a70a204dbc648968cf7c20 (diff) | |
- Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/amd8131')
| -rw-r--r-- | src/southbridge/amd/amd8131/amd8131_bridge.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index dc474fc7b0..357059d347 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -1,5 +1,5 @@ /* - * (C) 2003 Linux Networx + * (C) 2003-2004 Linux Networx */ #include <console/console.h> #include <device/device.h> @@ -106,20 +106,19 @@ static void ioapic_enable(device_t dev) value &= ~((1 << 1) | (1 << 0)); } pci_write_config32(dev, 0x44, value); - - /* We have to enable MEM and Bus Master for IOAPIC */ - value = pci_read_config32(dev, 0x4); - value |= 6; - pci_write_config32(dev, 0x4, value); } +static struct pci_operations pci_ops_pci_dev = { + .set_subsystem = pci_dev_set_subsystem, +}; static struct device_operations ioapic_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = ioapic_enable, + .init = 0, + .scan_bus = 0, + .enable = ioapic_enable, + .ops_pci = &pci_ops_pci_dev, }; static struct pci_driver ioapic_driver __pci_driver = { |