src/southbridge: Code formating

Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

5 files changed, 40 insertions, 40 deletions

diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 396b7c448a..2a6cf8d33d 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -152,7 +152,7 @@ static void acpi_init(struct device *dev)
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
-	if(on) {
+	if (on) {
 		pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
 		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 		inl(pm10_bar + 0x10);
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index 00f8f50add..bf0b03791f 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -26,11 +26,11 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 		if ((val & 0x800) == 0) {
 			break;
 		}
-		if(loops == (SMBUS_TIMEOUT / 2)) {
+		if (loops == (SMBUS_TIMEOUT / 2)) {
 			outw(inw(smbus_io_base + SMBGSTATUS),
 				smbus_io_base + SMBGSTATUS);
 		}
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
 
@@ -46,7 +46,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 		if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
 			break;
 		}
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 }
 
@@ -267,11 +267,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned
 	}
 
 	/* read data block */
-	for(i=0; i<msglen && i<bytes; i++) {
+	for (i=0; i<msglen && i<bytes; i++) {
 		buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
 	}
 	/* empty fifo */
-	while(bytes++<msglen) {
+	while (bytes++<msglen) {
 		inw(smbus_io_base + SMBHSTFIFO);
 	}
 
@@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne
 	outw(bytes, smbus_io_base + SMBHSTDAT);
 
 	/* set the data block */
-	for(i=0; i<bytes; i++) {
+	for (i=0; i<bytes; i++) {
 		outw(buf[i], smbus_io_base + SMBHSTFIFO);
 	}
 
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index ece99ed40a..d84ef182fe 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -4,16 +4,16 @@
 /* by yhlu 2005.10 */
 static unsigned get_sbdn(unsigned bus)
 {
-        device_t dev;
+	device_t dev;
 
-        /* Find the device.
-         * There can only be one 8111 on a hypertransport chain/bus.
-         */
-        dev = pci_locate_device_on_bus(
-                PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
-                bus);
+	/* Find the device.
+	 * There can only be one 8111 on a hypertransport chain/bus.
+	 */
+	dev = pci_locate_device_on_bus(
+		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+		bus);
 
-        return (dev>>15) & 0x1f;
+	return (dev>>15) & 0x1f;
 
 }
 
@@ -40,34 +40,34 @@ static void enable_cf9(void)
 
 void hard_reset(void)
 {
-        set_bios_reset();
-        /* reset */
-        enable_cf9();
-        outb(0x0e, 0x0cf9); // make sure cf9 is enabled
+	set_bios_reset();
+	/* reset */
+	enable_cf9();
+	outb(0x0e, 0x0cf9); // make sure cf9 is enabled
 }
 
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
-        device_t dev;
+	device_t dev;
 
 	dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
 
-        pci_write_config8(dev, 0x74, 4);
+	pci_write_config8(dev, 0x74, 4);
 
-        /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
-        pci_write_config32(dev, 0x70, 2<<12);
+	/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+	pci_write_config32(dev, 0x70, 2<<12);
 
 }
 
 static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 {
-        device_t dev;
+	device_t dev;
 
 	dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
 
-        /* Reset */
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
+	/* Reset */
+	set_bios_reset();
+	pci_write_config8(dev, 0x47, 1);
 
 }
 
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
index ef0cee1357..a7eee35659 100644
--- a/src/southbridge/amd/amd8111/ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
@@ -33,8 +33,8 @@ static void ide_init(struct device *dev)
 	pci_write_config16(dev, 0x40, word);
 
 
-        byte = 0x20 ; // Latency: 64-->32
-        pci_write_config8(dev, 0xd, byte);
+	byte = 0x20 ; // Latency: 64-->32
+	pci_write_config8(dev, 0xd, byte);
 
 	word = 0x0f;
 	pci_write_config16(dev, 0x42, word);
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index 8824550423..3cc1a0a5d3 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -12,26 +12,26 @@
 
 static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
 {
-        unsigned addr;
-        addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outb(value, 0xCFC + (addr & 3));
+	unsigned addr;
+	addr = (dev>>4) | where;
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	outb(value, 0xCFC + (addr & 3));
 }
 
 static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
 {
 	unsigned addr;
-        addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outl(value, 0xCFC);
+	addr = (dev>>4) | where;
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(value, 0xCFC);
 }
 
 static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
 {
 	unsigned addr;
-        addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        return inl(0xCFC);
+	addr = (dev>>4) | where;
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	return inl(0xCFC);
 }
 
 #define PCI_DEV_INVALID (0xffffffffU)
@@ -40,7 +40,7 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
 	pci_devfn_t dev, last;
 	dev = PCI_DEV(bus, 0, 0);
 	last = PCI_DEV(bus, 31, 7);
-	for(; dev <= last; dev += PCI_DEV(0,0,1)) {
+	for (; dev <= last; dev += PCI_DEV(0,0,1)) {
 		unsigned int id;
 		id = pci_read_config32(dev, 0);
 		if (id == pci_id) {