diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 15:59:51 +0100 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-20 18:59:44 +0000 |
commit | b274ccf59670c9110c75edbe563e6d5287d4604d (patch) | |
tree | 819ef70555d4eaaa49dc2633f09c78fd6b2d0099 /src/southbridge/amd/amd8111/early_ctrl.c | |
parent | f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 (diff) |
sb/amd/amd8111: Remove support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I5d7f3bfca47b86e4fd761f9462bc7297b487fdee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36964
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/amd8111/early_ctrl.c')
-rw-r--r-- | src/southbridge/amd/amd8111/early_ctrl.c | 100 |
1 files changed, 0 insertions, 100 deletions
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c deleted file mode 100644 index e9676ebc08..0000000000 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 yhlu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_ids.h> -#include <reset.h> -#include <southbridge/amd/common/reset.h> -#include "amd8111.h" - -unsigned int get_sbdn(unsigned int bus) -{ - pci_devfn_t dev; - - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), - bus); - - return (dev>>15) & 0x1f; - -} - -static void enable_cf9_x(unsigned int sbbusn, unsigned int sbdn) -{ - pci_devfn_t dev; - uint8_t byte; - - dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI - /* enable cf9 */ - byte = pci_read_config8(dev, 0x41); - byte |= (1<<6) | (1<<5); - pci_write_config8(dev, 0x41, byte); -} - -static void enable_cf9(void) -{ - unsigned int sblk = get_sblk(); - unsigned int sbbusn = get_sbbusn(sblk); - unsigned int sbdn = get_sbdn(sbbusn); - - enable_cf9_x(sbbusn, sbdn); -} - -void do_board_reset(void) -{ - set_bios_reset(); - /* reset */ - enable_cf9(); - outb(0x0e, 0x0cf9); // make sure cf9 is enabled -} - -void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn) -{ - pci_devfn_t dev; - - dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI - - pci_write_config8(dev, 0x74, 4); - - /* set VFSMAF (VID/FID System Management Action Field) to 2 */ - pci_write_config32(dev, 0x70, 2<<12); - -} - -static void soft_reset_x(unsigned int sbbusn, unsigned int sbdn) -{ - pci_devfn_t dev; - - dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA - - /* Reset */ - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); - -} - -void do_soft_reset(void) -{ - - unsigned int sblk = get_sblk(); - unsigned int sbbusn = get_sbbusn(sblk); - unsigned int sbdn = get_sbdn(sbbusn); - - return soft_reset_x(sbbusn, sbdn); - -} |