diff options
author | arch import user (historical) <svn@openbios.org> | 2005-07-06 16:48:04 +0000 |
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committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 16:48:04 +0000 |
commit | bc5be4791979056cad8a1f718984ba14d73904db (patch) | |
tree | e805e8a7b214a66021a77e7532f01aa1b85f28e7 /src/southbridge/amd/amd8111/amd8111_nic.c | |
parent | 4966de81c341aca7e2ae8f971a112acfaeba89b1 (diff) |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-4
Creator: Eric Biederman <ebiederman@lnxi.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/amd8111/amd8111_nic.c')
-rw-r--r-- | src/southbridge/amd/amd8111/amd8111_nic.c | 70 |
1 files changed, 67 insertions, 3 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c index b3792086a5..0a96d74577 100644 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -6,20 +6,84 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <arch/io.h> #include "amd8111.h" +#define CMD3 0x54 + +typedef enum { + VAL3 = (1 << 31), /* VAL bit for byte 3 */ + VAL2 = (1 << 23), /* VAL bit for byte 2 */ + VAL1 = (1 << 15), /* VAL bit for byte 1 */ + VAL0 = (1 << 7), /* VAL bit for byte 0 */ +}VAL_BITS; + +typedef enum { + /* VAL3 */ + ASF_INIT_DONE_ALIAS = (1 << 29), + /* VAL2 */ + JUMBO = (1 << 21), + VSIZE = (1 << 20), + VLONLY = (1 << 19), + VL_TAG_DEL = (1 << 18), + /* VAL1 */ + EN_PMGR = (1 << 14), + INTLEVEL = (1 << 13), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), + /* VAL0 */ + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), +}CMD3_BITS; + +static void nic_init(struct device *dev) +{ + struct southbridge_amd_amd8111_config *conf; + struct resource *resource; + unsigned long mmio; + + conf = dev->chip_info; + resource = find_resource(dev, PCI_BASE_ADDRESS_0); + mmio = resource->base; + + /* Hard Reset PHY */ + printk_debug("Reseting PHY... "); + if (conf->phy_lowreset) { + writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3)); + } else { + writel(VAL0 | RESET_PHY, (void *)(mmio + CMD3)); + } + mdelay(15); + writel(RESET_PHY, (void *)(mmio + CMD3)); + printk_debug("Done\n"); +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0xc8, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, + .init = nic_init, .scan_bus = 0, + .enable = amd8111_enable, + .ops_pci = &lops_pci, }; static struct pci_driver nic_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7462, + .device = PCI_DEVICE_ID_AMD_8111_NIC, }; |