- Bump the LinuxBIOS major version

- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 14 insertions, 4 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c
index a92274695d..167484401b 100644
--- a/src/southbridge/amd/amd8111/amd8111_ide.c
+++ b/src/southbridge/amd/amd8111/amd8111_ide.c
@@ -7,21 +7,21 @@
 
 static void ide_init(struct device *dev)
 {
-
+	struct southbridge_amd_amd8111_config *conf;
 	/* Enable ide devices so the linux ide driver will work */
 	uint16_t word;
 	uint8_t byte;
-	int enable_a=1, enable_b=1;
+	conf = dev->chip_info;
 
 	word = pci_read_config16(dev, 0x40);
 	/* Ensure prefetch is disabled */
 	word &= ~((1 << 15) | (1 << 13));
-	if (enable_b) {
+	if (conf->ide1_enable) {
 		/* Enable secondary ide interface */
 		word |= (1<<0);
 		printk_debug("IDE1 ");
 	}
-	if (enable_a) {
+	if (conf->ide0_enable) {
 		/* Enable primary ide interface */
 		word |= (1<<1);
 		printk_debug("IDE0 ");
@@ -40,12 +40,22 @@ static void ide_init(struct device *dev)
 	pci_write_config16(dev, 0x42, word);
 }
 
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x70, 
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+static struct pci_operations lops_pci = {
+	.set_subsystem = lpci_set_subsystem,
+};
 static struct device_operations ide_ops  = {
 	.read_resources   = pci_dev_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = ide_init,
 	.scan_bus         = 0,
+	.enable           = amd8111_enable,
+	.ops_pci          = &lops_pci
 };
 
 static struct pci_driver ide_driver __pci_driver = {