diff options
| author | Dave Frodin <dave.frodin@se-eng.com> | 2014-06-05 14:30:22 -0600 |
|---|---|---|
| committer | Dave Frodin <dave.frodin@se-eng.com> | 2014-06-11 20:06:21 +0200 |
| commit | ac1b875b554f45b0c98d375369119495b7ad2a2a (patch) | |
| tree | cb397c9fe4972193e4b95808c37cfc267f160401 /src/southbridge/amd/agesa | |
| parent | 61f902d4a7779d0ce30de79df7a71ad0c3788887 (diff) | |
amd/southbridge/lpc: SPI BAR has fixed size/location
The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.
Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd/agesa')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.h | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/lpc.c | 11 |
2 files changed, 9 insertions, 7 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 6f757eb72e..50f1738b4e 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,7 +51,9 @@ #define REV_HUDSON_A11 0x11 #define REV_HUDSON_A12 0x12 -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define SPI_ROM_ENABLE 0x02 +#define SPI_BASE_ADDRESS 0xFEC10000 #ifndef __SMM__ diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 71aaf6fe91..c8051ec42d 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -87,8 +87,6 @@ static void hudson_lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - pci_get_resource(dev, 0xA0); /* SPI ROM base address */ - /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; @@ -102,6 +100,9 @@ static void hudson_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Add a memory resource for the SPI BAR. */ + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); + res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; @@ -115,12 +116,10 @@ static void hudson_lpc_set_resources(struct device *dev) struct resource *res; /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); - res->base |= PCI_COMMAND_MEMORY; + res = find_resource(dev, 2); + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); pci_dev_set_resources(dev); - - } /** |