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| author | John Su <john_su@compal.corp-partner.google.com> | 2019-01-10 14:53:26 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 12:15:10 +0000 |
| commit | 3126964d969a43a042e4c18ebe5188b7e3d57209 (patch) | |
| tree | b313188915573ff1c8b325afd9241fcc320fc69c /src/southbridge/amd/agesa | |
| parent | 1d748c5346df116dad9b158d0874f7bdb3ef855f (diff) | |
soc/intel/cannonlake: Provide interface to update TCC offset
This change provides an interface for canonlake to set TCC.
With this change, we can add code to update Tcc in devicetree.
BUG=b:122636962
TEST=Match the result from TAT UI
Change-Id: Ib54a118e4e409919e3e60112e4621a109404b16d
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/southbridge/amd/agesa')
0 files changed, 0 insertions, 0 deletions