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authorFurquan Shaikh <furquan@chromium.org>2016-11-20 21:04:00 -0800
committerFurquan Shaikh <furquan@google.com>2016-11-22 17:32:09 +0100
commitc28984d9ea08e7d995ef9fc8064c10ec0c0d9d77 (patch)
treec113582c3d2d8fb8d54a4c9a53375340fcc302d5 /src/southbridge/amd/agesa/hudson
parent282c8322791800ee0d732fdaa5eb2cd8f7effd58 (diff)
spi: Clean up SPI flash driver interface
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson')
-rw-r--r--src/southbridge/amd/agesa/hudson/Kconfig1
-rw-r--r--src/southbridge/amd/agesa/hudson/spi.c43
2 files changed, 22 insertions, 22 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index fd79a3f034..eed83ae53f 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -64,6 +64,7 @@ config HUDSON_XHCI_FWM
config HUDSON_IMC_FWM
bool "Add imc firmware"
default y if USE_BLOBS
+ select SPI_FLASH_HAS_VOLATILE_GROUP if SPI_FLASH
help
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 31160bdcd9..f1a82e9022 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -17,17 +17,14 @@
#include <string.h>
#include <arch/io.h>
#include <console/console.h>
+#include <spi_flash.h>
#include <spi-generic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
-#if IS_ENABLED (CONFIG_HUDSON_IMC_FWM)
#include <Proc/Fch/FchPlatform.h>
-static int bus_claimed = 0;
-#endif
-
#define SPI_REG_OPCODE 0x0
#define SPI_REG_CNTRL01 0x1
#define SPI_REG_CNTRL02 0x2
@@ -149,32 +146,34 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return 0;
}
+
int spi_claim_bus(struct spi_slave *slave)
{
-#if IS_ENABLED (CONFIG_HUDSON_IMC_FWM)
+ /* Nothing is required. */
+ return 0;
+}
- if (slave->rw == SPI_WRITE_FLAG) {
- bus_claimed++;
- if (bus_claimed == 1)
- ImcSleep(NULL);
- }
-#endif
+void spi_release_bus(struct spi_slave *slave)
+{
+ /* Nothing is required. */
+}
+
+int chipset_volatile_group_begin(const struct spi_flash *flash)
+{
+ if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))
+ return 0;
+ ImcSleep(NULL);
return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+int chipset_volatile_group_end(const struct spi_flash *flash)
{
-#if IS_ENABLED (CONFIG_HUDSON_IMC_FWM)
-
- if (slave->rw == SPI_WRITE_FLAG) {
- bus_claimed--;
- if (bus_claimed <= 0) {
- bus_claimed = 0;
- ImcWakeup(NULL);
- }
- }
-#endif
+ if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))
+ return 0;
+
+ ImcWakeup(NULL);
+ return 0;
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)