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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-29 16:17:33 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-14 19:42:49 +0200
commit1110495de926db4b21b9969da522e5270c67f115 (patch)
tree04a04b6e797173c1b3639a4c4ecb90c544ab84ab /src/southbridge/amd/agesa/hudson
parent77d1280d0c866a9f85e62f74c43fe8d021a4ff39 (diff)
SPI: Split writes using spi_crop_chunk()
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson')
-rw-r--r--src/southbridge/amd/agesa/hudson/spi.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 720b26f83e..f050a63f91 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -42,6 +42,7 @@ static int bus_claimed = 0;
#define SPI_REG_CNTRL11 0xd
#define CNTRL11_FIFOPTR_MASK 0x07
+#define AMD_SB_SPI_TX_LEN 64
static u32 spibar;
@@ -86,6 +87,11 @@ void spi_init(void)
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
}
+unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
+{
+ return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len);
+}
+
int spi_xfer(struct spi_slave *slave, const void *dout,
unsigned int bytesout, void *din, unsigned int bytesin)
{