diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-10 10:00:38 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-14 15:23:30 +0000 |
| commit | 109a58a852e7e5517fcef001b941849772bb1363 (patch) | |
| tree | c59917ed5368252417fadabe4ffd229b5d219335 /src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | |
| parent | 76f5b225e216ffface3ce07d85bc46f9386480c7 (diff) | |
AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON
I refused bolton under agesa/ once it turned out to be
blobbed. We have AMD_PI_BOLTON.
Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 77d660cc4f..148bcccfc9 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -21,7 +21,7 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 @@ -51,8 +51,8 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define PIRQ_SD 0x17 /* SD */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ @@ -70,9 +70,7 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define PIRQ_SD 0x42 /* SD 14h.7 */ -#endif -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ |