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authorDuncan Laurie <dlaurie@chromium.org>2014-05-22 08:25:36 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-01-04 00:03:54 +0100
commit25c6f75bb29fceba7a30d170f2401241fc3428ed (patch)
treef05601525d0177b05a915a7243485f4967c28c22 /src/southbridge/Makefile.inc
parentfe8b788a12b225ae45ecb26625cfd2588d193ff3 (diff)
samus: Update for board revision 1.9
- Update GPIO map - Update SPD for new memory and 4-bit table decode - Enable USB3 port 3 and 4 (shared with PCIe port 1) - Enable PCIe port 3 and disable port 1 - Enable SerialIO ACPI mode for devices - Disable S0ix for now to prevent use of C10 - Special handling for memory with broadwell CPU BUG=chrome-os-partner:28234 TEST=Boot on P1.9 Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201083 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6 Reviewed-on: http://review.coreboot.org/8007 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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