diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2017-07-12 23:01:26 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-18 22:10:19 +0000 |
| commit | ff48b3b1ece1de71926a8f36ac71c1dddbc36b59 (patch) | |
| tree | c4f3c0be10ac856c3ac17266a123ffc7322e960f /src/soc | |
| parent | 27db0dd79027ee997a67cdf1fca37ea4dafe232b (diff) | |
soc/intel/skylake: Enable SMBus based on mainboard config
Enable SMBus controller based on config in mainboard devicetree.cb
BUG=None
TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run
lspci in OS) based on board devicetree.cb config 'SmbusEnable'.
Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 1c63250d1f..9e871254cb 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -237,6 +237,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + mainboard_memory_init_params(mupd); } |