driver/intel/fsp2_0: Add version parameter to FSP platform callback

Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

3 files changed, 3 insertions, 3 deletions

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index f1d4b57494..d623913086 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -237,7 +237,7 @@ static void fill_console_params(FSPM_UPD *mupd)
 	}
 }
 
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	fill_console_params(mupd);
 	mainboard_memory_init_params(mupd);
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index d90bd38d85..17080a3baf 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -87,7 +87,7 @@ int fill_power_state(void)
 	return ps->prev_sleep_state;
 }
 
-void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd)
+void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
 {
 	FSPM_ARCH_UPD *aupd;
 	const struct device *dev;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 8e083234a0..adb84423ac 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -132,7 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 	m_cfg->PcieRpEnableMask = mask;
 }
 
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;