diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2021-08-25 12:30:55 +0100 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-10-01 18:53:28 +0000 |
| commit | f71d8c94eadf269585691a0cebd635b23aa7e21d (patch) | |
| tree | a41f4eaf7222a8b8fade27c9b64a9347a4c8fdf4 /src/soc | |
| parent | 7a63f48a5439cffb8b8d5d3ac49fc64ddff0948b (diff) | |
soc/tigerlake: Make IO decode / enable register configurable
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 4 |
2 files changed, 20 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index f613a959e2..73514926ec 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -20,6 +20,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <soc/bootblock.h> +#include <soc/soc_chip.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/p2sb.h> @@ -108,9 +109,21 @@ void pch_early_iorange_init(void) uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; - /* IO Decode Range */ - if (CONFIG(DRIVERS_UART_8250IO)) - lpc_io_setup_comm_a_b(); + const uint16_t lpc_ioe_enable_mask = LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | + LPC_IOE_LPT_EN | LPC_IOE_FDD_EN | + LPC_IOE_LGE_200 | LPC_IOE_HGE_208 | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | + LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F; + + const config_t *config = config_of_soc(); + + if (config->lpc_ioe) { + io_enables = config->lpc_ioe & lpc_ioe_enable_mask; + } else { + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + } /* IO Decode Enable */ lpc_enable_fixed_io_ranges(io_enables); diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 966ce7c9c9..b63ff01fda 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/power_limit.h> #include <intelblocks/tcss.h> @@ -119,6 +120,9 @@ struct soc_intel_tigerlake_config { uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ + /* LPC fixed enables and ranges */ + uint32_t lpc_ioe; + /* Generic IO decode ranges */ uint32_t gen1_dec; uint32_t gen2_dec; |