intel: Use CF9 reset (part 2)

Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().

Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.

We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.

Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.

Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

17 files changed, 65 insertions, 41 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 81709422d0..1872ed0feb 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -104,7 +104,8 @@ config CPU_SPECIFIC_OPTIONS
 	select PLATFORM_USES_FSP2_0
 	select UDK_2015_BINDING if !SOC_INTEL_GLK
 	select UDK_2017_BINDING if SOC_INTEL_GLK
-	select HAVE_HARD_RESET
+	select SOC_INTEL_COMMON_RESET
+	select HAVE_CF9_RESET_PREPARE
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select HAVE_FSP_GOP
 	select NO_UART_ON_SUPERIO
@@ -130,10 +131,6 @@ config TPM_ON_FAST_SPI
 	 TPM part is conntected on Fast SPI interface, but the LPC MMIO
 	 TPM transactions are decoded and serialized over the SPI interface.
 
-config SOC_INTEL_COMMON_RESET
-	bool
-	default y
-
 config PCR_BASE_ADDRESS
 	hex
 	default 0xd0000000
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 6ea7a5998e..36bf77b240 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -13,12 +13,13 @@
  * GNU General Public License for more details.
  */
 
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <delay.h>
 #include <fsp/util.h>
 #include <intelblocks/pmclib.h>
-#include <reset.h>
 #include <soc/heci.h>
+#include <soc/intel/common/reset.h>
 #include <soc/pm.h>
 #include <timer.h>
 
@@ -27,10 +28,10 @@
 void do_global_reset(void)
 {
 	pmc_global_reset_enable(1);
-	hard_reset();
+	do_full_reset();
 }
 
-void soc_reset_prepare(enum reset_type reset_type)
+void cf9_reset_prepare(void)
 {
 	struct stopwatch sw;
 
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 995564d717..d2ec6c1fa8 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -24,6 +24,7 @@
 #include <bootmode.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/pae.h>
@@ -38,7 +39,6 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/pmclib.h>
 #include <mrc_cache.h>
-#include <reset.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/meminit.h>
@@ -285,7 +285,7 @@ static void check_full_retrain(const FSPM_UPD *mupd)
 
 	if (ps->gen_pmcon1 & WARM_RESET_STS) {
 		printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");
-		hard_reset();
+		full_reset();
 	}
 }
 
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 2799e5b9af..2ba79926ea 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
-	select HAVE_HARD_RESET
 	select NO_FIXED_XIP_ROM_SIZE
 	select PARALLEL_MP
 	select PCIEXP_ASPM
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index ce830f354b..abe029a194 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
-	select HAVE_HARD_RESET
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c
index eae94cf6c5..a6f8092908 100644
--- a/src/soc/intel/cannonlake/reset.c
+++ b/src/soc/intel/cannonlake/reset.c
@@ -13,11 +13,12 @@
  * GNU General Public License for more details.
  */
 
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <fsp/util.h>
-#include <reset.h>
+#include <soc/intel/common/reset.h>
 #include <string.h>
 #include <timer.h>
 #include <soc/pci_devs.h>
@@ -85,7 +86,7 @@ void do_global_reset(void)
 
 	/* global reset if CSE fail to reset */
 	pmc_global_reset_enable(1);
-	hard_reset();
+	do_full_reset();
 }
 
 void chipset_handle_reset(uint32_t status)
@@ -93,7 +94,7 @@ void chipset_handle_reset(uint32_t status)
 	switch (status) {
 	case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
 		printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
-		do_global_reset();
+		global_reset();
 		break;
 	default:
 		printk(BIOS_ERR, "unhandled reset type %x\n", status);
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index ea6f10e1f6..42043d740d 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -25,6 +25,7 @@ config DISPLAY_SMM_MEMORY_MAP
 config SOC_INTEL_COMMON_RESET
 	bool
 	default n
+	select HAVE_CF9_RESET
 
 config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	bool
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index c2f0594283..870e371233 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -18,7 +18,7 @@
 #include <arch/smp/mpspec.h>
 #include <bootstate.h>
 #include <cbmem.h>
-#include <cpu/intel/reset.h>
+#include <cf9_reset.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/smm.h>
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index bdd7d9198e..71a7b0f02b 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -1,9 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright 2017 Google, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,21 +13,24 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/hlt.h>
-#include <arch/io.h>
-#include <cpu/intel/reset.h>
+#include <arch/cache.h>
+#include <cf9_reset.h>
+#include <console/console.h>
+#include <halt.h>
 #include <reset.h>
 
-#if IS_ENABLED(CONFIG_HAVE_HARD_RESET)
-void do_hard_reset(void)
+#include "reset.h"
+
+void global_reset(void)
 {
-	/* S0->S5->S0 trip. */
-	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+	printk(BIOS_INFO, "%s() called!\n", __func__);
+	cf9_reset_prepare();
+	dcache_clean_all();
+	do_global_reset();
+	halt();
 }
-#endif
 
-void do_soft_reset(void)
+void do_board_reset(void)
 {
-	/* PMC_PLTRST# asserted. */
-	outb(RST_CPU | SYS_RST, RST_CNT);
+	full_reset();
 }
diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h
new file mode 100644
index 0000000000..0e605d6c61
--- /dev/null
+++ b/src/soc/intel/common/reset.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _INTEL_COMMON_RESET_H_
+#define _INTEL_COMMON_RESET_H_
+
+/*
+ * Implement SoC specific global reset (i.e. a reset of both host and
+ * ME partitions). Usually the ME is asked to perform the reset first.
+ * If that doesn't work out, fall back to a manual global reset.
+ */
+void do_global_reset(void);
+
+/* Prepare for reset, run do_global_reset(), halt. */
+__noreturn void global_reset(void);
+
+#endif	/* _INTEL_COMMON_RESET_H_ */
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index e22b8ee081..736d567c17 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_RESET
 	select PLATFORM_USES_FSP2_0
-	select HAVE_HARD_RESET
 	select POSTCAR_STAGE
 	select C_ENVIRONMENT_BOOTBLOCK
 	select IOAPIC
diff --git a/src/soc/intel/denverton_ns/reset.c b/src/soc/intel/denverton_ns/reset.c
index 97955a574a..577f1c4914 100644
--- a/src/soc/intel/denverton_ns/reset.c
+++ b/src/soc/intel/denverton_ns/reset.c
@@ -15,13 +15,12 @@
 
 #include <console/console.h>
 #include <fsp/util.h>
-#include <reset.h>
 
 void chipset_handle_reset(uint32_t status)
 {
 	switch (status) {
 	case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */
-		global_reset();
+		die("Global Reset not implemented!\n");
 		break;
 	default:
 		printk(BIOS_ERR, "unhandled reset type %x\n", status);
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index cf4ae7c1ed..617b64a619 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -15,9 +15,9 @@
  */
 
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
-#include <reset.h>
 #include <soc/fiamux.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -93,7 +93,7 @@ static void early_pmc_init(void)
 				pci_write_config32(dev, PMC_ETR3,
 					pci_read_config32(dev, PMC_ETR3)
 					| PMC_ETR3_CF9GR);
-				hard_reset();
+				full_reset();
 			}
 		}
 	}
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 30bb6a2740..232dc4fcc0 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_VERSTAGE_X86_32
 	select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP
 	select C_ENVIRONMENT_BOOTBLOCK
-	select HAVE_HARD_RESET
 	select HAVE_MONOTONIC_TIMER
 	select NO_MMCONF_SUPPORT
 	select REG_SCRIPT
diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c
index b5b86f3489..fe133663a8 100644
--- a/src/soc/intel/quark/reset.c
+++ b/src/soc/intel/quark/reset.c
@@ -13,13 +13,13 @@
  * GNU General Public License for more details.
  */
 
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <fsp/util.h>
-#include <reset.h>
 
 void chipset_handle_reset(uint32_t status)
 {
 	/* Do a hard reset if Quark FSP ever requests a reset */
 	printk(BIOS_ERR, "Unknown reset type %x\n", status);
-	hard_reset();
+	full_reset();
 }
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index f7a46bef8d..1452b57d1f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -31,7 +31,6 @@ config CPU_SPECIFIC_OPTIONS
 	select C_ENVIRONMENT_BOOTBLOCK
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
-	select HAVE_HARD_RESET
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
index d9e3ea5062..f73563e05e 100644
--- a/src/soc/intel/skylake/reset.c
+++ b/src/soc/intel/skylake/reset.c
@@ -13,10 +13,11 @@
  * GNU General Public License for more details.
  */
 
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <intelblocks/pmclib.h>
-#include <reset.h>
+#include <soc/intel/common/reset.h>
 #include <soc/me.h>
 #include <soc/pm.h>
 #include <timer.h>
@@ -32,7 +33,7 @@ static void do_force_global_reset(void)
 
 	/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
 	 * to global reset platform */
-	hard_reset();
+	do_full_reset();
 }
 
 void do_global_reset(void)