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authorDaisuke Nojiri <dnojiri@chromium.org>2014-02-27 14:56:39 -0800
committerMarc Jones <marc.jones@se-eng.com>2014-12-17 04:53:05 +0100
commitf574a327eed82ce00ea94d3f904f3dd8001d240c (patch)
tree61083257eb1013a8043a6569e483316b44e6f1f1 /src/soc
parent032c84381751bab0fe1da2e963af41cbe52c303d (diff)
ARM: Use LPAE for Virtual Address Translation
This change introduces LPAE for virtual address translation. To enable it, set ARM_LPAE. Boot slows down about 4ms on Tegra124 with LPAE enabled. TEST=Booted nyan with and without LPAE. Built nyan_big and daisy. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I74aa729b6fe6d243f57123dc792302359c661cad Original-Reviewed-on: https://chromium-review.googlesource.com/187862 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 6d8c8b2bbdc70555076081eb3bfaabde7b4a398f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8980375c14758af35f7d5ec5244be963e5462d8a Reviewed-on: http://review.coreboot.org/7749 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra124/Kconfig17
1 files changed, 7 insertions, 10 deletions
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 7862dd5b7b..195261e2e4 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -1,4 +1,6 @@
config SOC_NVIDIA_TEGRA124
+ bool
+ default n
select ARCH_BOOTBLOCK_ARMV4
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
@@ -6,8 +8,8 @@ config SOC_NVIDIA_TEGRA124
select BOOTBLOCK_CONSOLE
select DYNAMIC_CBMEM
select ARM_BOOTBLOCK_CUSTOM
- bool
- default n
+ select ARM_LPAE
+
if SOC_NVIDIA_TEGRA124
@@ -31,8 +33,7 @@ config BOOTBLOCK_CPU_INIT
# handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
#
# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
-# 0x4000_4020 CBMEM console area (8K-32B)
-# 0x4000_6000 CBFS mapping cache (88K)
+# 0x4000_4020 CBFS mapping cache (96K-32B)
# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
# 0x4002_0000 Bootblock (max 48KB).
# 0x4002_C000 ROM stage (max 80KB).
@@ -86,15 +87,11 @@ config TTB_BUFFER
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
- default 0x40006000
+ default 0x40004020
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
- default 0x00016000
-
-config CBMEM_CONSOLE_PRERAM_BASE
- hex "memory address of the CBMEM console buffer"
- default 0x40004020
+ default 0x00017fe0
config TEGRA124_MODEL_TD570D
bool "TD570D"