diff options
| author | Usha P <usha.p@intel.com> | 2022-01-18 13:37:15 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-26 16:20:48 +0000 |
| commit | f1b11e7fcc36d1e9023aba642796dc924cb35288 (patch) | |
| tree | 818c8123dab0ac2223caabd96ddcd9e324cf7f64 /src/soc | |
| parent | 707aa2ae77b2b5bded91c0c963b8a9112ab9ac6b (diff) | |
soc/intel/alderlake: Add GPIO Controller device ID for ADL-N
Add PCH ACPI Device ID for Alder Lake N SOC GPIO Controller.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I6eb15751dd303b4b445cb64f25a040302e50c09d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/gpio.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h index acaade449d..407c3b757f 100644 --- a/src/soc/intel/alderlake/include/soc/gpio.h +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -6,8 +6,13 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define CROS_GPIO_NAME "INTC1057" +#define CROS_GPIO_DEVICE_NAME "INTC1057:00" +#else #define CROS_GPIO_NAME "INTC1055" #define CROS_GPIO_DEVICE_NAME "INTC1055:00" +#endif /* Enable GPIO community power management configuration */ #define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \ |