diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-04-28 23:32:01 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-21 14:04:24 +0000 |
| commit | e5ca71db06a539d30f83d5fdf920e24ef4891df5 (patch) | |
| tree | 4a2ce829c27efc766a068d6cd85d63d487799a9e /src/soc | |
| parent | 88019ddbdf367ce8e44fd46d46ad042f9ca78355 (diff) | |
soc/intel/common: Add support to read CPU and PCH Trace Hub modes
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.
For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/basecode/debug/debug_feature.c | 27 | ||||
| -rw-r--r-- | src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h | 3 |
2 files changed, 29 insertions, 1 deletions
diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c index 64919346f8..d048abf81d 100644 --- a/src/soc/intel/common/basecode/debug/debug_feature.c +++ b/src/soc/intel/common/basecode/debug/debug_feature.c @@ -9,9 +9,22 @@ #define DEBUG_FEATURE_CTRL_SZ 64 #define SI_DESC_REGION_SZ 4096 +#define DEBUG_FEATURE_UNDEFINED 0xff struct debug_feature_cntrl { uint8_t cse_fw_update_disable; /* Byte location: 0xF00 */ - uint8_t reserved[63]; + + /* + * Supported CPU Trace Hub modes: + * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode + */ + uint8_t cpu_tracehub_mode; /* Byte location: 0xF01 */ + + /* + * Supported PCH Trace Hub modes: + * 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode + */ + uint8_t pch_tracehub_mode; /* Byte location: 0xF02 */ + uint8_t reserved[61]; }; static struct debug_feature_cntrl dbg_feature_cntrl; @@ -20,6 +33,18 @@ _Static_assert(sizeof(struct debug_feature_cntrl) % 64 == 0 && sizeof(struct debug_feature_cntrl) <= 256, "sizeof(struct debug_feature_cntrl) must be a multiple of 64 bytes and up to 256 bytes"); +void debug_get_pch_cpu_tracehub_modes(uint8_t *cpu_tracehub_mode, uint8_t *pch_tracehub_mode) +{ + if (dbg_feature_cntrl.pch_tracehub_mode != DEBUG_FEATURE_UNDEFINED) + *pch_tracehub_mode = dbg_feature_cntrl.pch_tracehub_mode; + + if (dbg_feature_cntrl.cpu_tracehub_mode != DEBUG_FEATURE_UNDEFINED) + *cpu_tracehub_mode = dbg_feature_cntrl.cpu_tracehub_mode; + + printk(BIOS_DEBUG, "rt_debug: CPU Trace Hub Mode: %d PCH Trace Hub Mode: %d\n", + *pch_tracehub_mode, *cpu_tracehub_mode); +} + bool is_debug_cse_fw_update_disable(void) { printk(BIOS_DEBUG, "rt_debug: dbg_feature_cntrl.cse_fw_update_disable=%d\n", diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h index c8e23822d2..9a01590fcb 100644 --- a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h +++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h @@ -5,6 +5,9 @@ #include <types.h> +/* Get cpu and pch tracehub modes defined in the OEM Section of descriptor region */ +void debug_get_pch_cpu_tracehub_modes(uint8_t *cpu_tracehub_mode, uint8_t *pch_trachub_mode); + /* Check if CSE firmware update is enabled or not */ bool is_debug_cse_fw_update_disable(void); |