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authorRavi Sarawadi <ravishankar.sarawadi@intel.com>2022-10-31 13:06:47 -0700
committerFelix Held <felix-coreboot@felixheld.de>2022-11-08 14:13:17 +0000
commitdf1aea1f2a13ea3fbee6ea2c9d4137ba3ee762b8 (patch)
treeb7f1b220389dea94dc261bba25adf2e9dce566bb /src/soc
parentfeab4a4dff60dd7e3b9406123779144521300041 (diff)
soc/intel/meteorlake: Remove PM Energy Report WA
Disable Pch PM Energy Report WA was added to enhance boot time with HFPGA only. SoC needs reporting enabled. BUG=None TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression.. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/meteorlake/fsp_params.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 4fd8f79533..4fe2f63ddf 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -375,14 +375,6 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
s_cfg->PsOnEnable = 1;
/* Enable the energy efficient turbo mode */
s_cfg->EnergyEfficientTurbo = 1;
-
- /*
- * UPDATEME: This is WA for HFPGA
- * Disable Pch Pm Energy Report
- * Energy Report is disabled to enhance boottime with HFPGA.
- */
- s_cfg->PchPmDisableEnergyReport = 1;
-
s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask();
}