diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:46:44 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:41:09 +0000 |
| commit | d9802111122d6273c711eccd352d29d7f34ba4e2 (patch) | |
| tree | c98f9aff4f07069b4fa72f74dcba48cf06514a70 /src/soc | |
| parent | eb5147027e974ba365aa4706935c7c9582cf7619 (diff) | |
soc/intel/fsp_baytrail: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc')
68 files changed, 0 insertions, 11298 deletions
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig deleted file mode 100644 index 5a8bec995b..0000000000 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ /dev/null @@ -1,117 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOC_INTEL_FSP_BAYTRAIL - bool - help - Bay Trail I part support using the Intel FSP. - -if SOC_INTEL_FSP_BAYTRAIL - -config CPU_SPECIFIC_OPTIONS - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON_RESET - select NO_RELOCATABLE_RAMSTAGE - select PARALLEL_MP - select REG_SCRIPT - select SMP - select SPI_FLASH - select SSE2 - select TSC_SYNC_MFENCE - select UDELAY_TSC - select TSC_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_HOOKED_UP - select INTEL_DESCRIPTOR_MODE_CAPABLE - select HAVE_SPI_CONSOLE_SUPPORT - select DRIVERS_I2C_DESIGNWARE - - # Microcode header files are delivered in FSP package - select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN - -config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE - -config SOC_INTEL_FSP_BAYTRAIL_MD - bool - default n - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/fsp_baytrail/bootblock/bootblock.c" - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - -config MAX_CPUS - int - default 4 - -config CPU_ADDR_BITS - int - default 36 - -config SMM_TSEG_SIZE - hex - default 0x800000 - help - This is set by the FSP - -config SMM_RESERVED_SIZE - hex - default 0x100000 - -config VGA_BIOS_ID - string - default "8086,0f31" - help - This is the default PCI ID for the Bay Trail graphics - devices. This string names the vbios ROM in cbfs. - -config ENABLE_BUILTIN_COM1 - bool "Enable built-in legacy Serial Port" - help - The Baytrail SOC has one legacy serial port. Choose this option to - configure the pads and enable it. This serial port can be used for - the debug console. - -config VGA_BIOS_FILE - string - default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS - -config CPU_MICROCODE_HEADER_FILES - string - default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" - -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config SOC_INTEL_I2C_DEV_MAX - int - default 7 - -## Baytrail Specific FSP Kconfig -source src/soc/intel/fsp_baytrail/fsp/Kconfig - -endif #SOC_INTEL_FSP_BAYTRAIL diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc deleted file mode 100644 index 0d89832f7d..0000000000 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2010 Google Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -# Copyright (C) 2016-2019 Siemens AG -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_SOC_INTEL_FSP_BAYTRAIL),y) - -subdirs-y += fsp -subdirs-y += romstage -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/cache -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../lib/fsp - -romstage-y += gpio.c -romstage-y += iosf.c -romstage-y += memmap.c -romstage-y += pmutil.c -romstage-y += spi.c -romstage-y += tsc_freq.c -romstage-y += i2c.c - -postcar-y += tsc_freq.c - -ramstage-y += acpi.c -ramstage-y += chip.c -ramstage-y += cpu.c -ramstage-y += gfx.c -ramstage-y += gpio.c -ramstage-y += i2c.c -ramstage-y += iosf.c -ramstage-y += lpe.c -ramstage-y += lpss.c -ramstage-y += memmap.c -ramstage-y += northcluster.c -ramstage-y += pmutil.c -ramstage-y += ramstage.c -ramstage-y += southcluster.c -ramstage-y += spi.c -ramstage-y += tsc_freq.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c - -smm-y += pmutil.c -smm-y += smihandler.c -smm-y += spi.c -smm-y += tsc_freq.c - -# Remove as ramstage gets fleshed out -ramstage-y += placeholders.c - -CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include -CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp - -endif diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c deleted file mode 100644 index 5efa82f3b7..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/speedstep.h> -#include <cpu/intel/turbo.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/baytrail.h> -#include <soc/pci_devs.h> -#include <soc/acpi.h> -#include <string.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pmc.h> -#include <soc/irq.h> -#include <soc/iosf.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <soc/msr.h> -#include <soc/pattrs.h> -#include <cbmem.h> -#include <version.h> - -#include "chip.h" - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -/* C-state map without S0ix */ -static acpi_cstate_t cstate_map[] = { - { - /* C1 */ - .ctype = 1, /* ACPI C1 */ - .latency = 1, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - { - /* C6NS with no L2 shrink */ - /* NOTE: this substate is above CPUID limit */ - .ctype = 2, /* ACPI C2 */ - .latency = 500, - .power = 10, - .resource = MWAIT_RES(5, 1), - }, - { - /* C6FS with full L2 shrink */ - .ctype = 3, /* ACPI C3 */ - .latency = 1500, /* 1.5ms worst case */ - .power = 10, - .resource = MWAIT_RES(5, 2), - } -}; - -void acpi_init_gnvs(global_nvs_t *gnvs) -{ - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - - /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = nc_read_top_of_low_memory(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif -} - -static int acpi_sci_irq(void) -{ - u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); - int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq; - - /* Determine how SCI is routed. */ - scis = read32(actl) & SCIS_MASK; - switch (scis) { - case SCIS_IRQ9: - case SCIS_IRQ10: - case SCIS_IRQ11: - sci_irq = scis - SCIS_IRQ9 + 9; - break; - case SCIS_IRQ20: - case SCIS_IRQ21: - case SCIS_IRQ22: - case SCIS_IRQ23: - sci_irq = scis - SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } - - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; -} - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); - return current; -} - -/** - * Fill in the fadt with generic values that can be overridden later. - */ - -typedef struct soc_intel_fsp_baytrail_config config_t; - -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC); - u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; - config_t *config = config_of(lpcdev); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - - /* - * Reference section 5.2.9 Fixed ACPI Description Table (FADT) - * in the ACPI 3.0b specification. - */ - - /* FADT Header Structure */ - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = asl_revision; - - /* ACPI Pointers */ - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - - fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ - - /* System Management */ - fadt->sci_int = acpi_sci_irq(); - - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - - /* Power Control */ - fadt->s4bios_req = 0x00; - fadt->pstate_cnt = 0x00; - - /* Control Registers - Base Address */ - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x00; /* Not Used */ - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x00; /* Not Used */ - fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0x00; /* Not Used */ - - /* Control Registers - Length */ - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 0; - - /* RTC Registers */ - fadt->day_alrm = 0x0D; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = config->fadt_boot_arch; /* legacy free default */ - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ - - /* Extended ACPI Pointers */ - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0x00; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0x00; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; - - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} -static acpi_tstate_t baytrail_tss_table[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1e, 0 }, - { 75, 750, 0, 0x1c, 0 }, - { 63, 625, 0, 0x1a, 0 }, - { 50, 500, 0, 0x18, 0 }, - { 38, 375, 0, 0x16, 0 }, - { 25, 250, 0, 0x14, 0 }, - { 13, 125, 0, 0x12, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set NVS controlled T-state limit */ - acpigen_write_TPC("\\TLVL"); - - /* Write TSS table for MSR access */ - acpigen_write_TSS_package( - ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - int vid, vid_turbo, vid_min, vid_max, vid_range_2; - u32 control_status; - const struct pattrs *pattrs = pattrs_get(); - msr_t msr; - - /* Inputs from CPU attributes */ - ratio_max = pattrs->iacore_ratios[IACORE_MAX]; - ratio_min = pattrs->iacore_ratios[IACORE_LFM]; - vid_max = pattrs->iacore_vids[IACORE_MAX]; - vid_min = pattrs->iacore_vids[IACORE_LFM]; - - /* Hardware coordination of P-states */ - coord_type = HW_ALL; - - /* Max Non-Turbo Frequency */ - clock_max = (ratio_max * pattrs->bclk_khz) / 1000; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (msr.lo & 0xf); - msr = rdmsr(MSR_PKG_POWER_LIMIT); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with NVS specified limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = 1; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > 15) { /* ACPI max is 15 ratios */ - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; - vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; - control_status = (ratio_turbo << 8) | vid_turbo; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - ratio_turbo = ratio_max; - vid_turbo = vid_max; - } - - /* First regular entry is max non-turbo ratio */ - control_status = (ratio_max << 8) | vid_max; - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control */ - control_status); /*status*/ - - /* Set up ratio and vid ranges for VID calculation */ - ratio_range_2 = (ratio_turbo - ratio_min) * 2; - vid_range_2 = (vid_turbo - vid_min) * 2; - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate VID for this ratio */ - vid = ((ratio - ratio_min) * vid_range_2) / - ratio_range_2 + vid_min; - /* Round up if remainder */ - if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) - vid++; - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = (ratio * pattrs->bclk_khz) / 1000; - control_status = (ratio << 8) | (vid & 0xff); - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(struct device *device) -{ - int core; - int pcontrol_blk = get_pmbase(), plen = 6; - const struct pattrs *pattrs = pattrs_get(); - - for (core=0; core<pattrs->num_cpus; core++) { - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_PR.CPUx */ - acpigen_write_processor( - core, pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - core, pattrs->num_cpus); - - /* Generate C-state tables */ - acpigen_write_CST_package( - cstate_map, ARRAY_SIZE(cstate_map)); - - /* Generate T-state tables */ - generate_T_state_entries( - core, pattrs->num_cpus); - - acpigen_pop_len(); - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(pattrs->num_cpus); -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) -{ - int sci_irq = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); - - return current; -} - -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_header_t *ssdt2; - - current = acpi_write_hpet(device, current, rsdp); - current = acpi_align_current(current); - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - current = acpi_align_current(current); - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - - return current; -} - -void southcluster_inject_dsdt(struct device *device) -{ - global_nvs_t *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); - if (gnvs) - memset(gnvs, 0, sizeof(*gnvs)); - } - - if (gnvs) { - acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); - - /* Add it to DSDT. */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); - acpigen_pop_len(); - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl b/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl deleted file mode 100644 index 54978cd2c0..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/device_nvs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Device Enabled in ACPI Mode */ - -S0EN, 8, // SDMA Enable -S1EN, 8, // I2C1 Enable -S2EN, 8, // I2C2 Enable -S3EN, 8, // I2C3 Enable -S4EN, 8, // I2C4 Enable -S5EN, 8, // I2C5 Enable -S6EN, 8, // I2C6 Enable -S7EN, 8, // I2C7 Enable -S8EN, 8, // SDMA2 Enable -S9EN, 8, // SPI Enable -SAEN, 8, // PWM1 Enable -SBEN, 8, // PWM2 Enable -SCEN, 8, // UART2 Enable -SDEN, 8, // UART2 Enable -C0EN, 8, // MMC Enable -C1EN, 8, // SDIO Enable -C2EN, 8, // SD Card Enable -LPEN, 8, // LPE Enable - -/* BAR 0 */ - -S0B0, 32, // SDMA BAR0 -S1B0, 32, // I2C1 BAR0 -S2B0, 32, // I2C2 BAR0 -S3B0, 32, // I2C3 BAR0 -S4B0, 32, // I2C4 BAR0 -S5B0, 32, // I2C5 BAR0 -S6B0, 32, // I2C6 BAR0 -S7B0, 32, // I2C7 BAR0 -S8B0, 32, // SDMA2 BAR0 -S9B0, 32, // SPI BAR0 -SAB0, 32, // PWM1 BAR0 -SBB0, 32, // PWM2 BAR0 -SCB0, 32, // UART1 BAR0 -SDB0, 32, // UART2 BAR0 -C0B0, 32, // MMC BAR0 -C1B0, 32, // SDIO BAR0 -C2B0, 32, // SD Card BAR0 -LPB0, 32, // LPE BAR0 - -/* BAR 1 */ - -S0B1, 32, // SDMA BAR1 -S1B1, 32, // I2C1 BAR1 -S2B1, 32, // I2C2 BAR1 -S3B1, 32, // I2C3 BAR1 -S4B1, 32, // I2C4 BAR1 -S5B1, 32, // I2C5 BAR1 -S6B1, 32, // I2C6 BAR1 -S7B1, 32, // I2C7 BAR1 -S8B1, 32, // SDMA2 BAR1 -S9B1, 32, // SPI BAR1 -SAB1, 32, // PWM1 BAR1 -SBB1, 32, // PWM2 BAR1 -SCB1, 32, // UART1 BAR1 -SDB1, 32, // UART2 BAR1 -C0B1, 32, // MMC BAR1 -C1B1, 32, // SDIO BAR1 -C2B1, 32, // SD Card BAR1 -LPB1, 32, // LPE BAR1 - -/* Extra */ - -LPFW, 32, // LPE BAR2 Firmware diff --git a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl deleted file mode 100644 index c4d91a3c16..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 - -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - - /* Device Config */ - Offset (0x20), - S5U0, 8, // 0x20 - Enable USB0 in S5 - S5U1, 8, // 0x21 - Enable USB1 in S5 - S3U0, 8, // 0x22 - Enable USB0 in S3 - S3U1, 8, // 0x23 - Enable USB1 in S3 - TACT, 8, // 0x24 - Thermal Active trip point - TPSV, 8, // 0x25 - Thermal Passive trip point - TCRT, 8, // 0x26 - Thermal Critical trip point - DPTE, 8, // 0x27 - Enable DPTF - - /* Base addresses */ - Offset (0x30), - CMEM, 32, // 0x30 - CBMEM TOC - TOLM, 32, // 0x34 - Top of Low Memory - CBMC, 32, // 0x38 - coreboot mem console pointer - - Offset (0x1000), - #include <soc/intel/fsp_baytrail/acpi/device_nvs.asl> -} - -/* Set flag to enable USB charging in S3 */ -Method (S3UE) -{ - Store (One, \S3U0) - Store (One, \S3U1) -} - -/* Set flag to disable USB charging in S3 */ -Method (S3UD) -{ - Store (Zero, \S3U0) - Store (Zero, \S3U1) -} - -/* Set flag to enable USB charging in S5 */ -Method (S5UE) -{ - Store (One, \S5U0) - Store (One, \S5U1) -} - -/* Set flag to disable USB charging in S5 */ -Method (S5UD) -{ - Store (Zero, \S5U0) - Store (Zero, \S5U1) -} diff --git a/src/soc/intel/fsp_baytrail/acpi/gpio.asl b/src/soc/intel/fsp_baytrail/acpi/gpio.asl deleted file mode 100644 index d0e9be5366..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/gpio.asl +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/intel/fsp_baytrail/include/soc/iomap.h> -#include <soc/intel/fsp_baytrail/include/soc/irq.h> - -/* SouthCluster GPIO */ -Device (GPSC) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 1) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_SC_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - Return (0xF) - } -} - -/* NorthCluster GPIO */ -Device (GPNC) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 2) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_NC_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - Return (0xF) - } -} - -/* SUS GPIO */ -Device (GPSS) -{ - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") - Name (_UID, 3) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) - { - GPIO_SUS_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - Return (0xF) - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h b/src/soc/intel/fsp_baytrail/acpi/irq_helper.h deleted file mode 100644 index 8d18aeaeb3..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/irq_helper.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronics Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/* - * This file intentionally gets included multiple times, to set pic and apic - * modes, so should not have guard statements added. - */ - -/* - * This file will use arch/x86/acpi/irqroute.asl and mainboard/irqroute.h - * to generate the ACPI IRQ routing for the mainboard being compiled. - * This method uses #defines in irqroute.h along with the macros contained - * in this file to generate an IRQ routing for each PCI device in the system. - */ - -#undef PCI_DEV_PIRQ_ROUTES -#undef ACPI_DEV_IRQ -#undef PCI_DEV_PIRQ_ROUTE -#undef PIRQ_PIC_ROUTES -#undef PIRQ_PIC -#undef IRQROUTE_H -#undef ROOTPORT_METHODS -#undef RP_METHOD -#undef ROOTPORT_IRQ_ROUTES -#undef RP_IRQ_ROUTES - -#if defined(PIC_MODE) - -#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ - Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } - -#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ -Name(prefix_ ## func_ ## P, Package() \ -{ \ - ACPI_DEV_IRQ(0x0000, 0, a_), \ - ACPI_DEV_IRQ(0x0000, 1, b_), \ - ACPI_DEV_IRQ(0x0000, 2, c_), \ - ACPI_DEV_IRQ(0x0000, 3, d_), \ -}) - -/* define as blank so ROOTPORT_METHODS only gets inserted once */ -#define ROOTPORT_METHODS(prefix_, dev_) - -#else /* defined(PIC_MODE) */ - -#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ - Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } - -#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ -Name(prefix_ ## func_ ## A, Package() \ -{ \ - ACPI_DEV_IRQ(0x0000, 0, a_), \ - ACPI_DEV_IRQ(0x0000, 1, b_), \ - ACPI_DEV_IRQ(0x0000, 2, c_), \ - ACPI_DEV_IRQ(0x0000, 3, d_), \ -}) - -#define ROOTPORT_METHODS(prefix_, dev_) \ - RP_METHOD(prefix_, dev_, 0) \ - RP_METHOD(prefix_, dev_, 1) \ - RP_METHOD(prefix_, dev_, 2) \ - RP_METHOD(prefix_, dev_, 3) \ - RP_METHOD(prefix_, dev_, 4) \ - RP_METHOD(prefix_, dev_, 5) \ - RP_METHOD(prefix_, dev_, 6) \ - RP_METHOD(prefix_, dev_, 7) - -#endif /* defined(PIC_MODE) */ - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - ACPI_DEV_IRQ(dev_, 0, a_), \ - ACPI_DEV_IRQ(dev_, 1, b_), \ - ACPI_DEV_IRQ(dev_, 2, c_), \ - ACPI_DEV_IRQ(dev_, 3, d_) - -#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ - ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ - ROOTPORT_METHODS(prefix_, dev_) - -#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ - RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \ - RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \ - RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \ - RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \ - RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \ - RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \ - RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \ - RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) - -#define RP_METHOD(prefix_, dev_, func_)\ -Device(prefix_ ## 0 ## func_) \ -{ \ - Name(_ADR, dev_ ## 000 ## func_) \ - Name(_PRW, Package() { \ - 0, 0 \ - }) \ - Method(_PRT,0) { \ - If(PICM) { \ - Return (prefix_ ## func_ ## A) \ - } Else { \ - Return (prefix_ ## func_ ## P) \ - } \ - } \ -} - -/* Empty PIRQ_PIC definition. */ -#define PIRQ_PIC(pirq_, pic_irq_) - -/* Include the mainboard irq route definition */ -#include "irqroute.h" diff --git a/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl b/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl deleted file mode 100644 index 2d029242d8..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/irqlinks.asl +++ /dev/null @@ -1,487 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ(Level, ActiveLow, Shared) {} - }) - CreateWordField(RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField(Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit(IRQ0, Local0) - - Decrement(Local0) - Store(Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And(PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl deleted file mode 100644 index 4f3a744ff5..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// PCI Interrupt Routing -Method(_PRT) -{ - /* - * PICM comes from _PIC, which returns the following: - * 0 - PIC mode - * 1 - APIC mode - * 2 - SAPIC mode - */ - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include "irq_helper.h" - PCI_DEV_PIRQ_ROUTES - }) - } Else { - Return (Package() { - #define PIC_MODE - #include "irq_helper.h" - PCI_DEV_PIRQ_ROUTES - }) - } - -} - -PCIE_BRIDGE_IRQ_ROUTES -#undef PIC_MODE -#include "irq_helper.h" -PCIE_BRIDGE_IRQ_ROUTES diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl deleted file mode 100644 index 7cdf1aa5d0..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Intel LPC Bus Device - 0:1f.0 - -Device (LPCB) -{ - Name(_ADR, 0x001f0000) - - #include "irqlinks.asl" - - #include "acpi/ec.asl" - - Device (DMAC) // DMA Controller - { - Name(_HID, EISAID("PNP0200")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x00, 0x00, 0x01, 0x20) - IO (Decode16, 0x81, 0x81, 0x01, 0x11) - IO (Decode16, 0x93, 0x93, 0x01, 0x0d) - IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } - }) - } - - Device (FWH) // Firmware Hub - { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Method (_STA, 0) // Device Status - { - Return (0xf) // Enable and show device - } - - Name(_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400) - }) - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - - Name (RBUF, ResourceTemplate() - { - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - }) - - Method (_CRS, 0, NotSerialized) - { - Return (RBUF) - } - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - - // Include mainboard's superio.asl file. - #include "acpi/superio.asl" -} diff --git a/src/soc/intel/fsp_baytrail/acpi/lpe.asl b/src/soc/intel/fsp_baytrail/acpi/lpe.asl deleted file mode 100644 index d1dbd3a4b2..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/lpe.asl +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (LPEA) -{ - Name (_HID, "80860F28") - Name (_CID, "80860F28") - Name (_UID, 1) - Name (_DDN, "Low Power Audio Controller") - Name (_PR0, Package () { PLPE }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) - Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) - Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_DMA0_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_DMA1_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_SSP0_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_SSP1_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_SSP2_IRQ - } - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPE_IPC2HOST_IRQ - } - }) - - Method (_CRS) - { - /* Update BAR0 from NVS */ - CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) - Store (\LPB0, BAS0) - - /* Update BAR1 from NVS */ - CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) - Store (\LPB1, BAS1) - - /* Update LPE FW from NVS */ - CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) - Store (\LPFW, BAS2) - - /* Append any Mainboard defined GPIOs */ - If (CondRefOf (^GBUF, Local0)) { - ConcatenateResTemplate (^RBUF, Local0, Local1) - Return (Local1) - } - - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\LPEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, LPB1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - PowerResource (PLPE, 0, 0) - { - Method (_STA) - { - Return (1) - } - - Method (_OFF) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_ON) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/lpss.asl b/src/soc/intel/fsp_baytrail/acpi/lpss.asl deleted file mode 100644 index 6cac06a13e..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/lpss.asl +++ /dev/null @@ -1,707 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (SDM1) -{ - Name (_HID, "INTL9C60") - Name (_UID, 1) - Name (_DDN, "DMA Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_DMA1_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S0B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S0EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (SDM2) -{ - Name (_HID, "INTL9C60") - Name (_UID, 2) - Name (_DDN, "DMA Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_DMA2_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S8B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S8EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (I2C1) -{ - Name (_HID, "80860F41") - Name (_UID, 1) - Name (_DDN, "I2C Controller #1") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C1_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S1B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C2) -{ - Name (_HID, "80860F41") - Name (_UID, 2) - Name (_DDN, "I2C Controller #2") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C2_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S2B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C3) -{ - Name (_HID, "80860F41") - Name (_UID, 3) - Name (_DDN, "I2C Controller #3") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C3_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S3B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S3EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S3B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C4) -{ - Name (_HID, "80860F41") - Name (_UID, 4) - Name (_DDN, "I2C Controller #4") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C4_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S4B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S4EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S4B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C5) -{ - Name (_HID, "80860F41") - Name (_UID, 5) - Name (_DDN, "I2C Controller #5") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C5_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S5B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S5EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S5B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C6) -{ - Name (_HID, "80860F41") - Name (_UID, 6) - Name (_DDN, "I2C Controller #6") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C6_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S6B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S6B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (I2C7) -{ - Name (_HID, "80860F41") - Name (_UID, 7) - Name (_DDN, "I2C Controller #7") - - /* Standard Mode: HCNT, LCNT, SDA Hold Time */ - Name (SSCN, Package () { 0x200, 0x200, 0x6 }) - - /* Fast Mode: HCNT, LCNT, SDA Hold Time */ - Name (FMCN, Package () { 0x55, 0x99, 0x6 }) - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_I2C7_IRQ - } - FixedDMA (0x10, 0x0, Width32Bit, ) - FixedDMA (0x11, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S7B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S7EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S7B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (SPI1) -{ - Name (_HID, "80860F0E") - Name (_UID, 1) - Name (_DDN, "SPI Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_SPI_IRQ - } - FixedDMA (0x0, 0x0, Width32Bit, ) - FixedDMA (0x1, 0x1, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S9B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\S9EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, S9B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (PWM1) -{ - Name (_HID, "80860F09") - Name (_UID, 1) - Name (_DDN, "PWM Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SAB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SAEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (PWM2) -{ - Name (_HID, "80860F09") - Name (_UID, 2) - Name (_DDN, "PWM Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SBB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SBEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } -} - -Device (UAR1) -{ - Name (_HID, "80860F0A") - Name (_UID, 1) - Name (_DDN, "HS-UART Controller #1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_HSUART1_IRQ - } - FixedDMA (0x2, 0x2, Width32Bit, ) - FixedDMA (0x3, 0x3, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SCB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SCEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, SCB1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (UAR2) -{ - Name (_HID, "80860F0A") - Name (_UID, 2) - Name (_DDN, "HS-UART Controller #2") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - LPSS_HSUART2_IRQ - } - FixedDMA (0x4, 0x4, Width32Bit, ) - FixedDMA (0x5, 0x5, Width32Bit, ) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SDB0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\SDEN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, SDB1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/platform.asl b/src/soc/intel/fsp_baytrail/acpi/platform.asl deleted file mode 100644 index 01be3514fd..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/platform.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/common/acpi/platform.asl> - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/soc/intel/fsp_baytrail/acpi/scc.asl b/src/soc/intel/fsp_baytrail/acpi/scc.asl deleted file mode 100644 index c26511c751..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/scc.asl +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (EMMC) -{ - Name (_HID, "80860F14") - Name (_CID, "PNP0D40") - Name (_UID, 1) - Name (_DDN, "eMMC Controller 4.5") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_EMMC_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C0B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\C0EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, C0B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Device (EM45) - { - /* Slot 0, Function 8 */ - Name (_ADR, 0x8) - - Method (_RMV, 0, NotSerialized) - { - Return (0) - } - } -} - -Device (SDIO) -{ - Name (_HID, "INT33BB") - Name (_CID, "PNP0D40") - Name (_UID, 2) - Name (_DDN, "SDIO Controller") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_SDIO_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C1B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\C1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, C1B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} - -Device (SDCD) -{ - Name (_HID, "80860F16") - Name (_CID, "PNP0D40") - Name (_UID, 3) - Name (_DDN, "SD Card Controller") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_SD_IRQ - } - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C2B0, RBAS) - Return (^RBUF) - } - - Method (_STA) - { - If (LEqual (\C2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - OperationRegion (KEYS, SystemMemory, C2B1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - Method (_PS3) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_PS0) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl deleted file mode 100644 index ef4523b004..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/intel/fsp_baytrail/include/soc/iomap.h> -#include <soc/intel/fsp_baytrail/include/soc/irq.h> -#include "../include/soc/baytrail.h" - -Scope(\) -{ - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - - // Intel Legacy Block - OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) - Field (ILBS, AnyAcc, NoLock, Preserve) - { - Offset (0x8), - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - } -} - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -Name (MCRS, ResourceTemplate() -{ - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - - // High PCI Memory Region - QwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, UMEM) -}) - -Method (_CRS, 0, Serialized) -{ - // Update PCI resource area - CreateDwordField(MCRS, ^PMEM._MIN, PMIN) - CreateDwordField(MCRS, ^PMEM._MAX, PMAX) - CreateDwordField(MCRS, ^PMEM._LEN, PLEN) - - // TOLM is BMBOUND accessible from IOSF so is saved in NVS - Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add (Subtract (PMAX, PMIN), 1, PLEN) - - // Update High PCI resource area - CreateQwordField(MCRS, ^UMEM._MIN, UMIN) - CreateQwordField(MCRS, ^UMEM._MAX, UMAX) - CreateQwordField(MCRS, ^UMEM._LEN, ULEN) - - Store(0x40000000 * 48, UMIN) // Set base address to 48GB - Store(0x40000000 * 16, ULEN) // Allocate 16GB for PCI space - Add(UMIN, Subtract(ULEN, 1), UMAX) - - Return (MCRS) -} - -/* Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) - Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) - Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) - Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) - Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) - Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) - Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return(PDRS) - } -} - -Method (_OSC, 4) -{ - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} - -/* IOSF MBI Interface for kernel access */ -Device (IOSF) -{ - Name (_HID, "INT33BD") - Name (_CID, "INT33BD") - Name (_UID, 1) - - Name (RBUF, ResourceTemplate () - { - /* MCR / MDR / MCRX */ - Memory32Fixed (ReadWrite, 0, 12, RBAR) - }) - - Method (_CRS) - { - CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) - Return (^RBUF) - } -} - -// LPC Bridge 0:1f.0 -#include "lpc.asl" - -#if INCLUDE_EHCI -// USB EHCI 0:1d.0 -#include "usb.asl" -#endif - -#if INCLUDE_XHCI -// USB XHCI 0:14.0 -#include "xhci.asl" -#endif - -// IRQ routing for each PCI device -#include "irqroute.asl" - -Scope (\_SB) -{ - // GPIO Devices - #include "gpio.asl" - -#if INCLUDE_LPSS - // LPSS Devices - #include "lpss.asl" -#endif - -#if INCLUDE_SCC - // SCC Devices - #include "scc.asl" -#endif - -#if INCLUDE_LPE - // LPE Device - #include "lpe.asl" -#endif -} diff --git a/src/soc/intel/fsp_baytrail/acpi/usb.asl b/src/soc/intel/fsp_baytrail/acpi/usb.asl deleted file mode 100644 index c60bfcec46..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/usb.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel Baytrail USB support */ - -// EHCI Controller 0:1d.0 - -Device (EHC1) -{ - Name(_ADR, 0x001d0000) - - Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake - - // Leave USB ports on for to allow Wake from USB - - Method(_S3D,0) // Highest D State in S3 State - { - Return (2) - } - - Method(_S4D,0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0x00000000) - - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - } -} diff --git a/src/soc/intel/fsp_baytrail/acpi/xhci.asl b/src/soc/intel/fsp_baytrail/acpi/xhci.asl deleted file mode 100644 index dbd34474f8..0000000000 --- a/src/soc/intel/fsp_baytrail/acpi/xhci.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Device (XHCI) -{ - Name (_ADR, 0x00140000) - Name (_PRW, Package () { 0x0d, 3 }) - Name (_S3D, 3) /* Highest D state in S3 state */ - - Device (RHUB) - { - Name (_ADR, 0x00000000) - Device (PRT1) { Name (_ADR, 1) } - Device (PRT2) { Name (_ADR, 2) } - Device (PRT3) { Name (_ADR, 3) } - Device (PRT4) { Name (_ADR, 4) } - } -} diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c deleted file mode 100644 index 5351a0162f..0000000000 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/intel/microcode/microcode.c> -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/spi.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/gpio.h> - -/* - * check for a warm reset and do a hard reset instead. - */ -static void check_for_warm_reset(void) -{ - - /* - * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. - * If either is true, then this is a warm reset so execute a Hard Reset - */ - if ((inb(0xcf9) == 0x04) || - (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE)) { - outb(0x00, 0xcf9); - outb(0x06, 0xcf9); - } -} - -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - /* Enable caching and prefetching in the SPI controller. */ - write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void setup_mmconfig(void) -{ - uint32_t reg; - - /* Set up the MMCONF range. The register lives in the BUNIT. The - * IO variant of the config access needs to be used initially to - * properly configure as the IOSF access registers live in PCI - * config space. */ - reg = 0; - /* Clear the extended register. */ - pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; - pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | - IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; - pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); -} - -static const uint8_t lpc_pads[12] = { - 70, 68, 67, 66, 69, 71, 65, 72, 86, 90, 88, 92, -}; - -static void set_up_lpc_pads(void) -{ - uint32_t reg = IO_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, IOBASE, reg); - - for (reg = 0; reg < 12; reg++) - score_select_func(lpc_pads[reg], 1); -} - -static void bootblock_cpu_init(void) -{ - check_for_warm_reset(); - - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - - /* Allow memory-mapped PCI config access. */ - setup_mmconfig(); - enable_rom_caching(); - enable_spi_prefetch(); - set_up_lpc_pads(); -} diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c deleted file mode 100644 index 3ca26add30..0000000000 --- a/src/soc/intel/fsp_baytrail/chip.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <drivers/intel/fsp1_0/fsp_util.h> -#include "chip.h" - -static void pci_domain_set_resources(struct device *dev) -{ - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = baytrail_init_cpus, - .scan_bus = NULL, -}; - -static void enable_dev(struct device *dev) -{ - printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", - dev_name(dev), dev->path.type); - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle south cluster enablement. */ - if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && - (dev->ops == NULL || dev->ops->enable == NULL)) { - southcluster_enable_dev(dev); - } - } -} - -/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ -static void soc_init(void *chip_info) -{ - baytrail_init_pre_device(); -} - -struct chip_operations soc_intel_fsp_baytrail_ops = { - CHIP_NAME("Intel BayTrail SoC") - .enable_dev = enable_dev, - .init = soc_init, -}; - -struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_dev_set_subsystem, -}; diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h deleted file mode 100644 index e3167885b2..0000000000 --- a/src/soc/intel/fsp_baytrail/chip.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014-2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FSP_BAYTRAIL_CHIP_H_ -#define _FSP_BAYTRAIL_CHIP_H_ - -#include <arch/acpi.h> -#include <drivers/intel/fsp1_0/fsp_values.h> -#include <drivers/i2c/designware/dw_i2c.h> - -/* The devicetree parser expects chip.h to reside directly in the path - * specified by the devicetree. */ - -struct soc_intel_fsp_baytrail_config { - -/* ***** UPD Configuration ***** */ - - /* Spd addresses */ - uint8_t PcdMrcInitSPDAddr1; - uint8_t PcdMrcInitSPDAddr2; - #define SPD_ADDR_DEFAULT UPD_SPD_ADDR_DEFAULT - #define SPD_ADDR_DISABLED UPD_SPD_ADDR_DISABLED - - /* SataMode - * NOTE: These are offset by 1 to set 0 as "use default". This is so that - * if the register value is not set in the devicetree.cb file, the default - * value gets used. This is fixed up in the chipset_fsp_util.c code. - * - * 0x0 "IDE" - * 0x1 "AHCI" - */ - uint8_t PcdSataMode; - #define SATA_MODE_DEFAULT UPD_DEFAULT - #define SATA_MODE_IDE INCREMENT_FOR_DEFAULT(0) - #define SATA_MODE_AHCI INCREMENT_FOR_DEFAULT(1) - - /* - * MrcInitMmioSize - * 0x400, "1.0 GB"s - * 0x600, "1.5 GB" - * 0x800, "2.0 GB" - */ - uint16_t PcdMrcInitMmioSize; - #define MMIO_SIZE_DEFAULT UPD_DEFAULT - #define MMIO_SIZE_1_0_GB INCREMENT_FOR_DEFAULT(0x400) - #define MMIO_SIZE_1_5_GB INCREMENT_FOR_DEFAULT(0x600) - #define MMIO_SIZE_2_0_GB INCREMENT_FOR_DEFAULT(0x800) - - /* - * eMMCBootMode - * NOTE: These are offset by 1 to set 0 as "use default". This is so that - * if the register value is not set in the devicetree.cb file, the default - * value gets used. This is fixed up in the chipset_fsp_util.c code - * - * 0x0 "Disabled" - * 0x1 "Auto" - * 0x2 "eMMC 4.1" - * 0x3 "eMMC 4.5" - */ - uint8_t PcdeMMCBootMode; - #define EMMC_USE_DEFAULT UPD_DEFAULT - #define EMMC_DISABLED UPD_DISABLE - #define EMMC_AUTO INCREMENT_FOR_DEFAULT(1) - #define EMMC_4_1 INCREMENT_FOR_DEFAULT(2) - #define EMMC_4_5 INCREMENT_FOR_DEFAULT(3) - #define EMMC_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE - - /* - * IgdDvmt50PreAlloc - * 0x01, "32 MB" - * 0x02, "64 MB" - * 0x03, "96 MB" - * 0x04, "128 MB" - * 0x05, "160 MB" - * 0x06, "192 MB" - * 0x07, "224 MB" - * 0x08, "256 MB" - * 0x09, "288 MB" - * 0x0A, "320 MB" - * 0x0B, "352 MB" - * 0x0C, "384 MB" - * 0x0D, "416 MB" - * 0x0E, "448 MB" - * 0x0F, "480 MB" - * 0x10, "512 MB" - */ - uint8_t PcdIgdDvmt50PreAlloc; - #define IGD_MEMSIZE_DEFAULT UPD_DEFAULT - #define IGD_MEMSIZE_32MB INCREMENT_FOR_DEFAULT(0x01) - #define IGD_MEMSIZE_64MB INCREMENT_FOR_DEFAULT(0x02) - #define IGD_MEMSIZE_96MB INCREMENT_FOR_DEFAULT(0x03) - #define IGD_MEMSIZE_128MB INCREMENT_FOR_DEFAULT(0x04) - #define IGD_MEMSIZE_160MB INCREMENT_FOR_DEFAULT(0x05) - #define IGD_MEMSIZE_192MB INCREMENT_FOR_DEFAULT(0x06) - #define IGD_MEMSIZE_224MB INCREMENT_FOR_DEFAULT(0x07) - #define IGD_MEMSIZE_256MB INCREMENT_FOR_DEFAULT(0x08) - #define IGD_MEMSIZE_288MB INCREMENT_FOR_DEFAULT(0x09) - #define IGD_MEMSIZE_320MB INCREMENT_FOR_DEFAULT(0x0A) - #define IGD_MEMSIZE_352MB INCREMENT_FOR_DEFAULT(0x0B) - #define IGD_MEMSIZE_384MB INCREMENT_FOR_DEFAULT(0x0C) - #define IGD_MEMSIZE_416MB INCREMENT_FOR_DEFAULT(0x0D) - #define IGD_MEMSIZE_448MB INCREMENT_FOR_DEFAULT(0x0E) - #define IGD_MEMSIZE_480MB INCREMENT_FOR_DEFAULT(0x0F) - #define IGD_MEMSIZE_512MB INCREMENT_FOR_DEFAULT(0x10) - #define IGD_MEMSIZE_MULTIPLIER 32 - - /* - * Selection 0x1 , "128 MB" - * Selection 0x2 , "256 MB" - * Selection 0x3 , "512 MB" - */ - uint8_t PcdApertureSize; - #define APERTURE_SIZE_DEFAULT UPD_DEFAULT - #define APERTURE_SIZE_128MB INCREMENT_FOR_DEFAULT(1) - #define APERTURE_SIZE_256MB INCREMENT_FOR_DEFAULT(2) - #define APERTURE_SIZE_512MB INCREMENT_FOR_DEFAULT(3) - #define APERTURE_SIZE_BASE 64 - - /* - * Selection 0x1 , "1 MB" - * Selection 0x2 , "2 MB" - */ - uint8_t PcdGttSize; - #define GTT_SIZE_DEFAULT UPD_DEFAULT - #define GTT_SIZE_1MB INCREMENT_FOR_DEFAULT(1) - #define GTT_SIZE_2MB INCREMENT_FOR_DEFAULT(2) - - /* - * Enable PCI Mode for LPSS SIO devices. - * If disabled, LPSS SIO devices will run in ACPI mode. - */ - uint8_t PcdLpssSioEnablePciMode; - #define LPSS_PCI_MODE_DEFAULT UPD_DEFAULT - #define LPSS_PCI_MODE_DISABLE UPD_DISABLE - #define LPSS_PCI_MODE_ENABLE UPD_ENABLE - - /* modifiers for various enables */ - uint8_t AzaliaAutoEnable; - #define AZALIA_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE - #define AZALIA_FSP_AUTO_ENABLE UPD_ENABLE - - uint8_t LpeAcpiModeEnable; - #define LPE_ACPI_MODE_DISABLED UPD_DISABLE - #define LPE_ACPI_MODE_ENABLED UPD_ENABLE - - uint32_t SerialDebugPortAddress; - #define SerialDebugPortAddress_DEFAULT UPD_DEFAULT - - uint8_t SerialDebugPortType; - #define SERIAL_DEBUG_PORT_DEFAULT UPD_DEFAULT - #define SERIAL_DEBUG_PORT_TYPE_NONE INCREMENT_FOR_DEFAULT(0) - #define SERIAL_DEBUG_PORT_TYPE_IO INCREMENT_FOR_DEFAULT(1) - #define SERIAL_DEBUG_PORT_TYPE_MMIO INCREMENT_FOR_DEFAULT(2) - - uint8_t PcdMrcDebugMsg; - #define MRC_DEBUG_MSG_DEFAULT UPD_DEFAULT - #define MRC_DEBUG_MSG_DISABLE UPD_DISABLE - #define MRC_DEBUG_MSG_ENABLE UPD_ENABLE - - uint8_t PcdSccEnablePciMode; - #define SCC_PCI_MODE_DEFAULT UPD_DEFAULT - #define SCC_PCI_MODE_DISABLE UPD_DISABLE - #define SCC_PCI_MODE_ENABLE UPD_ENABLE - - uint8_t IgdRenderStandby; - #define IGD_RENDER_STANDBY_DEFAULT UPD_DEFAULT - #define IGD_RENDER_STANDBY_DISABLE UPD_DISABLE - #define IGD_RENDER_STANDBY_ENABLE UPD_ENABLE - - uint8_t TxeUmaEnable; - #define TXE_UMA_DEFAULT UPD_DEFAULT - #define TXE_UMA_DISABLE UPD_DISABLE - #define TXE_UMA_ENABLE UPD_ENABLE - - /* - * PcdOsSelection - * Selection 0x1 , "Android" - * Selection 0x4 , "Linux OS" - */ - uint8_t PcdOsSelection; - #define OS_SELECTION_DEFAULT UPD_DEFAULT - #define OS_SELECTION_ANDROID INCREMENT_FOR_DEFAULT(1) - #define OS_SELECTION_LINUX INCREMENT_FOR_DEFAULT(4) - - /* PcdEMMC45DDR50Enabled */ - uint8_t PcdEMMC45DDR50Enabled; - #define EMMC45_DDR50_DEFAULT UPD_DEFAULT - #define EMMC45_DDR50_DISABLE UPD_DISABLE - #define EMMC45_DDR50_ENABLE UPD_ENABLE - - /* PcdEMMC45HS200Enabled */ - uint8_t PcdEMMC45HS200Enabled; - #define EMMC45_HS200_DEFAULT UPD_DEFAULT - #define EMMC45_HS200_DISABLE UPD_DISABLE - #define EMMC45_HS200_ENABLE UPD_ENABLE - - /* PcdEMMC45RetuneTimerValue */ - uint8_t PcdEMMC45RetuneTimerValue; - #define EMMC45_RETURN_TIMER_DEFAULT UPD_DEFAULT - - /* PcdEnableIgd */ - uint8_t PcdEnableIgd; - #define ENABLE_IGD_DEFAULT UPD_DEFAULT - #define ENABLE_IGD_DISABLE UPD_DISABLE - #define ENABLE_IGD_ENABLE UPD_ENABLE - - /* AutoSelfRefreshEnable */ - uint8_t AutoSelfRefreshEnable; - #define AUTO_SELF_REFRESH_DEFAULT UPD_DEFAULT - #define AUTO_SELF_REFRESH_DISABLE UPD_DISABLE - #define AUTO_SELF_REFRESH_ENABLE UPD_ENABLE - - /* APTaskTimeoutCnt */ - uint16_t APTaskTimeoutCnt; - #define AP_TASK_TIMEOUT_CNT_DEFAULT UPD_DEFAULT - - /* Memory down data */ - uint8_t EnableMemoryDown; - #define MEMORY_DOWN_DEFAULT UPD_DEFAULT - #define MEMORY_DOWN_DISABLE UPD_DISABLE - #define MEMORY_DOWN_ENABLE UPD_ENABLE - - /* - * PcdDRAMSpeed - * Selection 0x0 , "800 MHz" - * Selection 0x1 , "1066 MHz" - * Selection 0x2 , "1333 MHz" - * Selection 0x3 , "1600 MHz" - */ - uint8_t DRAMSpeed; - #define DRAM_SPEED_DEFAULT UPD_DEFAULT - #define DRAM_SPEED_800MHZ INCREMENT_FOR_DEFAULT(0) - #define DRAM_SPEED_1066MHZ INCREMENT_FOR_DEFAULT(1) - #define DRAM_SPEED_1333MHZ INCREMENT_FOR_DEFAULT(2) - #define DRAM_SPEED_1600MHZ INCREMENT_FOR_DEFAULT(3) - - /* - * PcdDRAMType - * Selection 0x0 , "DDR3" - * Selection 0x1 , "DDR3L" - * Selection 0x2 , "DDR3U" - * Selection 0x4 , "LPDDR2" - * Selection 0x5 , "LPDDR3" - * Selection 0x6 , "DDR4" - */ - uint8_t DRAMType; - #define DRAM_TYPE_DEFAULT UPD_DEFAULT - #define DRAM_TYPE_DDR3 INCREMENT_FOR_DEFAULT(0) - #define DRAM_TYPE_DDR3L INCREMENT_FOR_DEFAULT(1) - - uint8_t DIMM0Enable; - #define DIMM0_ENABLE_DEFAULT UPD_DEFAULT - #define DIMM0_DISABLE UPD_DISABLE - #define DIMM0_ENABLE UPD_ENABLE - - uint8_t DIMM1Enable; - #define DIMM1_ENABLE_DEFAULT UPD_DEFAULT - #define DIMM1_DISABLE UPD_DISABLE - #define DIMM1_ENABLE UPD_ENABLE - - /* - * PcdDIMMDWidth - * Selection 0x0 , "x8" - * Selection 0x1 , "x16" - * Selection 0x2 , "x32" - */ - uint8_t DIMMDWidth; - #define DIMM_DWIDTH_DEFAULT UPD_DEFAULT - #define DIMM_DWIDTH_X8 INCREMENT_FOR_DEFAULT(0) - #define DIMM_DWIDTH_X16 INCREMENT_FOR_DEFAULT(1) - #define DIMM_DWIDTH_X32 INCREMENT_FOR_DEFAULT(2) - - /* - * PcdDIMMDensity - * Selection 0x0 , "1 Gbit" - * Selection 0x1 , "2 Gbit" - * Selection 0x2 , "4 Gbit" - * Selection 0x3 , "8 Gbit" - */ - uint8_t DIMMDensity; - #define DIMM_DENSITY_DEFAULT UPD_DEFAULT - #define DIMM_DENSITY_1G_BIT INCREMENT_FOR_DEFAULT(0) - #define DIMM_DENSITY_2G_BIT INCREMENT_FOR_DEFAULT(1) - #define DIMM_DENSITY_4G_BIT INCREMENT_FOR_DEFAULT(2) - #define DIMM_DENSITY_8G_BIT INCREMENT_FOR_DEFAULT(3) - - /* - * PcdDIMMBusWidth - * Selection 0x0 , "8 bits" - * Selection 0x1 , "16 bits" - * Selection 0x2 , "32 bits" - * Selection 0x3 , "64 bits" - */ - uint8_t DIMMBusWidth; - #define DIMM_BUS_WIDTH_DEFAULT UPD_DEFAULT - #define DIMM_BUS_WIDTH_8BIT INCREMENT_FOR_DEFAULT(0) - #define DIMM_BUS_WIDTH_16BIT INCREMENT_FOR_DEFAULT(1) - #define DIMM_BUS_WIDTH_32BIT INCREMENT_FOR_DEFAULT(2) - #define DIMM_BUS_WIDTH_64BIT INCREMENT_FOR_DEFAULT(3) - - /* - * PcdDIMMSides - * Selection 0x0 , "1 Ranks" - * Selection 0x1 , "2 Ranks" - */ - uint8_t DIMMSides; - #define DIMM_SIDES_DEFAULT UPD_DEFAULT - #define DIMM_SIDES_1RANK INCREMENT_FOR_DEFAULT(0) - #define DIMM_SIDES_2RANK INCREMENT_FOR_DEFAULT(1) - - uint8_t DIMMtCL; - #define DIMM_TCL_DEFAULT UPD_DEFAULT - - uint8_t DIMMtRPtRCD; - #define DIMM_TRP_TRCD_DEFAULT UPD_DEFAULT - - uint8_t DIMMtWR; - #define DIMM_TWR_DEFAULT UPD_DEFAULT - - uint8_t DIMMtWTR; - #define DIMM_TWTR_DEFAULT UPD_DEFAULT - - uint8_t DIMMtRRD; - #define DIMM_TRRD_DEFAULT UPD_DEFAULT - - uint8_t DIMMtRTP; - #define DIMM_TRTP_DEFAULT UPD_DEFAULT - - uint8_t DIMMtFAW; - #define DIMM_TFAW_DEFAULT UPD_DEFAULT - - /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ - - /* Structure for designware I2C controller */ - struct dw_i2c_bus_config i2c[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - -/* ***** ACPI configuration ***** */ - /* Options for these are in src/arch/x86/include/arch/acpi.h */ - uint8_t fadt_pm_profile; - uint16_t fadt_boot_arch; - -}; - -#endif /* _FSP_BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c deleted file mode 100644 index 787a41015a..0000000000 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/microcode.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/turbo.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <reg_script.h> - -#include <soc/baytrail.h> -#include <soc/msr.h> -#include <soc/pattrs.h> -#include <soc/ramstage.h> -#include <soc/smm.h> - -/* Core level MSRs */ -static const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_MSR_OR(MSR_POWER_MISC, 0x44), - REG_SCRIPT_END -}; - -static void baytrail_core_init(struct device *cpu) -{ - printk(BIOS_DEBUG, "Init BayTrail core.\n"); - - /* On bay trail the turbo disable bit is actually scoped at building - * block level -- not package. For non-bsp cores that are within a - * building block enable turbo. The cores within the BSP's building - * block will just see it already enabled and move on. */ - if (lapicid()) - enable_turbo(); - - /* Set core MSRs */ - reg_script_run(core_msr_script); - - /* Set this core to max frequency ratio */ - set_max_freq(); -} - -static struct device_operations cpu_dev_ops = { - .init = baytrail_core_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x30671 }, - { X86_VENDOR_INTEL, 0x30672 }, - { X86_VENDOR_INTEL, 0x30673 }, - { X86_VENDOR_INTEL, 0x30678 }, - { X86_VENDOR_INTEL, 0x30679 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; - -/* - * MP and SMM loading initialization. - */ - -struct smm_relocation_params { - msr_t smrr_base; - msr_t smrr_mask; -}; - -static struct smm_relocation_params smm_reloc_params; - -static void pre_mp_init(void) -{ - x86_mtrr_check(); - - /* Enable the local CPU apics */ - setup_lapic(); -} - -static int get_cpu_count(void) -{ - const struct pattrs *pattrs = pattrs_get(); - - return pattrs->num_cpus; -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~(4 * KiB - 1); - - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; -} - -static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - const struct pattrs *pattrs = pattrs_get(); - - *microcode = pattrs->microcode_patch; - *parallel = 1; -} - -static void relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - struct smm_relocation_params *relo_params = &smm_reloc_params; - em64t100_smm_state_save_area_t *smm_state; - - /* Set up SMRR. */ - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); - - smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; -} - -static void enable_smis(void) -{ - if (CONFIG(HAVE_SMI_HANDLER)) - smm_southbridge_enable_smi(); -} - -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_cpu_count, - .get_smm_info = get_smm_info, - .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_southbridge_clear_state, - .relocation_handler = relocation_handler, - .post_mp_init = enable_smis, -}; - -void baytrail_init_cpus(struct device *dev) -{ - struct bus *cpu_bus = dev->link_list; - - if (mp_init_with_smm(cpu_bus, &mp_ops)) { - printk(BIOS_ERR, "MP initialization failure.\n"); - } -} diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig deleted file mode 100644 index 3fe358ec89..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config BAYTRAIL_FSP_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select USE_GENERIC_FSP_CAR_INC - select FSP_USES_UPD - -config FSP_FILE - string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex - default 0xfffc0000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - - The Bay Trail FSP is built with a preferred base address of - 0xFFFC0000. diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc deleted file mode 100644 index 024dd70855..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += chipset_fsp_util.c -ramstage-y += chipset_fsp_util.c diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c deleted file mode 100644 index 01c876d3b8..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014-2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <console/console.h> -#include <bootstate.h> -#include <cbmem.h> -#include <cf9_reset.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <soc/pci_devs.h> -#include <drivers/intel/fsp1_0/fsp_util.h> -#include "../chip.h" -#include <arch/io.h> -#include <soc/pmc.h> -#include <soc/acpi.h> -#include <soc/iomap.h> - -/* Copy the default UPD region and settings to a buffer for modification */ -static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - VPD_DATA_REGION *VpdDataRgnPtr; - UPD_DATA_REGION *UpdDataRgnPtr; - VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); - UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); -} - -/* default to just enabling HDMI audio */ -const PCH_AZALIA_CONFIG mAzaliaConfig = { - .Pme = 1, - .DS = 1, - .DA = 0, - .HdmiCodec = 1, - .AzaliaVCi = 1, - .Rsvdbits = 0, - .AzaliaVerbTableNum = 0, - .AzaliaVerbTable = NULL, - .ResetWaitTimer = 300 -}; - -typedef struct soc_intel_fsp_baytrail_config config_t; - -static const char *acpi_pci_mode_strings[] = { - "Disabled", - "Enabled in PCI Mode", - "Enabled in ACPI Mode" -}; - -static const char *emmc_mode_strings[] = { - "Disabled", - "Auto", - "eMMC 4.1", - "eMMC 4.5" -}; - -/** - * Update the UPD data based on values from devicetree.cb - * - * @param UpdData Pointer to the UPD Data structure - */ -static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - DEVTREE_CONST struct device *dev; - DEVTREE_CONST config_t *config; - printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); - - dev = pcidev_path_on_root(SOC_DEVFN_SOC); - config = config_of(dev); - - /* Set up default verb tables - Just HDMI audio */ - UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig; - - /* Set SPD addresses */ - UPD_SPD_CHECK(PcdMrcInitSPDAddr1); - UPD_SPD_CHECK(PcdMrcInitSPDAddr2); - - UPD_DEFAULT_CHECK(PcdSataMode); - UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode); - UPD_DEFAULT_CHECK(PcdMrcInitMmioSize); - UPD_DEFAULT_CHECK(PcdIgdDvmt50PreAlloc); - UPD_DEFAULT_CHECK(PcdApertureSize); - UPD_DEFAULT_CHECK(PcdGttSize); - UPD_DEFAULT_CHECK(SerialDebugPortAddress); - UPD_DEFAULT_CHECK(SerialDebugPortType); - UPD_DEFAULT_CHECK(PcdMrcDebugMsg); - UPD_DEFAULT_CHECK(PcdSccEnablePciMode); - UPD_DEFAULT_CHECK(IgdRenderStandby); - UPD_DEFAULT_CHECK(TxeUmaEnable); - UPD_DEFAULT_CHECK(PcdOsSelection); - UPD_DEFAULT_CHECK(PcdEMMC45DDR50Enabled); - UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled); - UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue); - UPD_DEFAULT_CHECK(PcdEnableIgd); - UPD_DEFAULT_CHECK(AutoSelfRefreshEnable); - UPD_DEFAULT_CHECK(APTaskTimeoutCnt); - - if (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE) - UpdData->PcdeMMCBootMode = 0; - else if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT)) - UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode - EMMC_DISABLED; - - UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20; - - printk(FSP_INFO_LEVEL, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); - printk(FSP_INFO_LEVEL, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); - printk(FSP_INFO_LEVEL, "Aperture Size:\t\t%d MB\n", - APERTURE_SIZE_BASE << UpdData->PcdApertureSize); - printk(FSP_INFO_LEVEL, "IGD Memory Size:\t%d MB\n", - UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER); - printk(FSP_INFO_LEVEL, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize); - - /* Advance dev to PCI device 0.0 */ - for (dev = &dev_root; dev; dev = dev_find_next_pci_device(dev)){ - if (dev->path.type != DEVICE_PATH_PCI) - continue; - if (dev->path.pci.devfn == PCI_DEVFN(0x0,0)) - break; - } - - /* - * Loop through all the SOC devices in the devicetree - * enabling and disabling them as requested. - */ - for (; dev; dev = dev->sibling) { - - if (dev->path.type != DEVICE_PATH_PCI) - continue; - - switch (dev->path.pci.devfn) { - UPD_DEVICE_CHECK(SOC_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t"); - UPD_DEVICE_CHECK(SOC_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t"); - - case SOC_DEVFN_MIPI: /* Camera / Image Signal Processing */ - if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { - UpdData->ISPEnable = dev->enabled; - } else { - /* Gold2 and earlier FSP: ISPEnable is the field */ - /* next to PcdGttSize in UPD_DATA_REGION struct */ - *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; - printk (FSP_INFO_LEVEL, - "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); - } - printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", - dev->enabled?"Enabled":"Disabled"); - break; - case SOC_DEVFN_EMMC: /* EMMC 4.1*/ - if ((dev->enabled) && - (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) - UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; - break; - case SOC_DEVFN_MMC45: /* MMC 4.5*/ - if ((dev->enabled) && - (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) - UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; - break; - case SOC_DEVFN_XHCI: - UpdData->PcdEnableXhci = dev->enabled; - break; - case SOC_DEVFN_EHCI: - UpdData->PcdEnableXhci = !(dev->enabled); - break; - - case SOC_DEVFN_LPE: - if (dev->enabled) - UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; - else - UpdData->PcdEnableLpe = 0; - break; - } - } - - if (UpdData->PcdEnableLpe < sizeof(acpi_pci_mode_strings) / sizeof (char *)) - printk(FSP_INFO_LEVEL, "Lpe:\t\t\t%s\n", - acpi_pci_mode_strings[UpdData->PcdEnableLpe]); - else - printk(FSP_INFO_LEVEL, "Lpe:\t\t\tUnknown (0x%02x)\n", - UpdData->PcdEnableLpe); - - if (UpdData->PcdeMMCBootMode < sizeof(emmc_mode_strings) / sizeof (char *)) - printk(FSP_INFO_LEVEL, "eMMC Mode:\t\t%s\n", - emmc_mode_strings[UpdData->PcdeMMCBootMode]); - else - printk(FSP_INFO_LEVEL, "eMMC Mode:\t\tUnknown (0x%02x)\n", - UpdData->PcdeMMCBootMode); - - - if (UpdData->PcdEnableSata) - printk(FSP_INFO_LEVEL, "SATA Mode:\t\t%s\n", - UpdData->PcdSataMode?"AHCI":"IDE"); - - printk(FSP_INFO_LEVEL, "Xhci:\t\t\t%s\n", - UpdData->PcdEnableXhci?"Enabled":"Disabled"); - - /* - * set memory down parameters - * Skip setting values if memory down is disabled - * Skip setting values if FSP is earlier than gold 3 - */ - if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { - UPD_MEMDOWN_CHECK(EnableMemoryDown, DECREMENT_FOR_DEFAULT); - if (UpdData->PcdMemoryParameters.EnableMemoryDown) { - UPD_MEMDOWN_CHECK(DRAMSpeed, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DRAMType, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMM0Enable, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMM1Enable, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMDWidth, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMDensity, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMBusWidth, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMSides, DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtCL, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtRPtRCD, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtWR, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtWTR, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtRRD, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtRTP, NO_DECREMENT_FOR_DEFAULT); - UPD_MEMDOWN_CHECK(DIMMtFAW, NO_DECREMENT_FOR_DEFAULT); - - printk (FSP_INFO_LEVEL, - "Memory Down Data Existed : %s\n"\ - "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ - "- Type (0: DDR3, 1: DDR3L) : %d\n"\ - "- DIMM0 : %s\n"\ - "- DIMM1 : %s\n"\ - "- Width : x%d\n"\ - "- Density : %dGbit\n" - "- BudWidth : %dbit\n"\ - "- Rank # : %d\n"\ - "- tCL : %02X\n"\ - "- tRPtRCD : %02X\n"\ - "- tWR : %02X\n"\ - "- tWTR : %02X\n"\ - "- tRRD : %02X\n"\ - "- tRTP : %02X\n"\ - "- tFAW : %02X\n" - , (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled" - , UpdData->PcdMemoryParameters.DRAMSpeed - , UpdData->PcdMemoryParameters.DRAMType - , (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled" - , (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled" - , 8 << (UpdData->PcdMemoryParameters.DIMMDWidth) - , 1 << (UpdData->PcdMemoryParameters.DIMMDensity) - , 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth) - , (UpdData->PcdMemoryParameters.DIMMSides) + 1 - , UpdData->PcdMemoryParameters.DIMMtCL - , UpdData->PcdMemoryParameters.DIMMtRPtRCD - , UpdData->PcdMemoryParameters.DIMMtWR - , UpdData->PcdMemoryParameters.DIMMtWTR - , UpdData->PcdMemoryParameters.DIMMtRRD - , UpdData->PcdMemoryParameters.DIMMtRTP - , UpdData->PcdMemoryParameters.DIMMtFAW - ); - } - } -} - -/* Set up the Baytrail specific structures for the call into the FSP */ -void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, - FSP_INFO_HEADER *fsp_ptr) -{ - FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; - uint32_t prev_sleep_state; - - /* Get previous sleep state but don't clear */ - prev_sleep_state = chipset_prev_sleep_state(0); - printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state); - - /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - pFspInitParams->NvsBufferPtr = NULL; - - /* Find the fastboot cache that was saved in the ROM */ - if (CONFIG(ENABLE_MRC_CACHE)) - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); - - if (prev_sleep_state == ACPI_S3) { - /* S3 resume */ - if (pFspInitParams->NvsBufferPtr == NULL) { - /* If waking from S3 and no cache then. */ - printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - /* Clear Sleep Type */ - outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & - ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); - /* Reboot */ - printk(BIOS_WARNING, "Rebooting..\n" ); - system_reset(); - /* Should not reach here.. */ - die("Reboot System\n"); - } - pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME; - } else { - /* Not S3 resume */ - pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; - } - - return; -} diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h deleted file mode 100644 index f75cc4e93d..0000000000 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CHIPSET_FSP_UTIL_H -#define CHIPSET_FSP_UTIL_H - -#include <fsp.h> -#include <fsptypes.h> -#include <fspfv.h> -#include <fspffs.h> -#include <fspapi.h> -#include <fspplatform.h> -#include <fspinfoheader.h> -#include <fsphob.h> -#include <fspvpd.h> -#include <azalia.h> - -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -/* - * The FSP Image ID is different for each platform's FSP and - * can be used to verify that the right FSP binary is loaded. - * For the Bay Trail FSP, the Image Id is "VLYVIEW0". - */ -#define FSP_IMAGE_ID_DWORD0 0x56594C56 /* 'VLYV' */ -#define FSP_IMAGE_ID_DWORD1 0x30574549 /* 'IEW0' */ - -/* Revision of the FSP binary */ -#define FSP_GOLD3_REV_ID 0x00000303 - -#define NO_DECREMENT_FOR_DEFAULT 0 -#define DECREMENT_FOR_DEFAULT 1 - -#define UPD_MEMDOWN_CHECK(member, adjust) \ - if (config->member != UPD_DEFAULT) { \ - UpdData->PcdMemoryParameters.member = config->member - adjust; \ - } - -#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c deleted file mode 100644 index dab997275d..0000000000 --- a/src/soc/intel/fsp_baytrail/gfx.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <reg_script.h> -#include <stdlib.h> -#include <soc/gfx.h> -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> - -#define GFX_TIMEOUT 100000 /* 100ms */ - -static const struct reg_script gpu_pre_vbios_script[] = { - /* Make sure GFX is bus master with MMIO access */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), - /* Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, - GFX_TIMEOUT), - /* Tx/Rx Lanes */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, - GFX_TIMEOUT), - /* Common Lane */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, - GFX_TIMEOUT), - /* Ungating Tx only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, - GFX_TIMEOUT), - /* Ungating Common Lane only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, - GFX_TIMEOUT), - /* Ungating Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, - GFX_TIMEOUT), - REG_SCRIPT_END -}; - -static const struct reg_script gfx_post_vbios_script[] = { - /* Deassert Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), - /* Deassert Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), - /* Set Lock bits */ - REG_PCI_RMW32(GGC, 0xffffffff, 1), - REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), - REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), - REG_SCRIPT_END -}; - -static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) -{ - reg_script_run_on_dev(dev, ops); -} - -static void gfx_pre_vbios_init(struct device *dev) -{ - printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); - gfx_run_script(dev, gpu_pre_vbios_script); -} - -static void gfx_post_vbios_init(struct device *dev) -{ - printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); - gfx_run_script(dev, gfx_post_vbios_script); -} - -static void gfx_init(struct device *dev) -{ - /* Pre VBIOS Init */ - gfx_pre_vbios_init(dev); - - /* Run VBIOS */ - pci_dev_init(dev); - - /* Post VBIOS Init */ - gfx_post_vbios_init(dev); -} - -static struct device_operations gfx_device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gfx_init, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver gfx_driver __pci_driver = { - .ops = &gfx_device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = GFX_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c deleted file mode 100644 index 3e2499accd..0000000000 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ /dev/null @@ -1,372 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <console/console.h> -#include <soc/gpio.h> -#include <soc/pmc.h> - -/* - * GPIO-to-Pad LUTs - * - * These tables translate the GPIO number to the pad configuration register - * for that GPIO in the memory-mapped pad configuration registers. - * See the tables: - * PCU iLB GPIO CFIO_SCORE Address Map - * PCU iLB GPIO CFIO_SSUS Address Map - */ -static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = - { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ - 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ - 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ - 2, 5, 9 }; /* [24:26] */ - -static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = - { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ - 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ - 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ - 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ - 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ - 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ - 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ - 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ - 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ - 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ - 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ - 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ - 106, 87, 91, 104, 97, 100 }; /* [96:101] */ - -static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = - { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ - 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ - 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ - 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ - 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ - 52, 53, 59, 40 }; /* [40:43] */ - - -/* GPIO bank descriptions */ -static const struct gpio_bank gpncore_bank = { - .gpio_count = GPNCORE_COUNT, - .gpio_to_pad = gpncore_gpio_to_pad, - .legacy_base = GP_LEGACY_BASE_NONE, - .pad_base = GPNCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, -}; - -static const struct gpio_bank gpscore_bank = { - .gpio_count = GPSCORE_COUNT, - .gpio_to_pad = gpscore_gpio_to_pad, - .legacy_base = GPSCORE_LEGACY_BASE, - .pad_base = GPSCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, -}; - -static const struct gpio_bank gpssus_bank = { - .gpio_count = GPSSUS_COUNT, - .gpio_to_pad = gpssus_gpio_to_pad, - .legacy_base = GPSSUS_LEGACY_BASE, - .pad_base = GPSSUS_PAD_BASE, - .has_wake_en = 1, - .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, -}; - - -static void setup_gpios(const struct soc_gpio_map *gpios, - const struct gpio_bank *bank) -{ - const struct soc_gpio_map *config; - int gpio = 0; - u32 reg, pad_conf0, *regmmio; - u8 set, bit; - - u32 use_sel[4] = {0}; - u32 io_sel[4] = {0}; - u32 gp_lvl[4] = {0}; - u32 tpe[4] = {0}; - u32 tne[4] = {0}; - u32 wake_en[4] = {0}; - - if (!gpios) - return; - - for (config = gpios; config->pad_conf0 != GPIO_LIST_END; - config++, gpio++) { - if (gpio > bank->gpio_count) - break; - - set = gpio >> 5; - bit = gpio % 32; - - if (bank->legacy_base != GP_LEGACY_BASE_NONE) { - /* Legacy IO configuration */ - use_sel[set] |= config->use_sel << bit; - io_sel[set] |= config->io_sel << bit; - gp_lvl[set] |= config->gp_lvl << bit; - tpe[set] |= config->tpe << bit; - tne[set] |= config->tne << bit; - - /* Some banks do not have wake_en ability */ - if (bank->has_wake_en) - wake_en[set] |= config->wake_en << bit; - } - - /* Pad configuration registers */ - regmmio = (u32 *)(bank->pad_base + 16 * - bank->gpio_to_pad[gpio]); - - /* Add correct func to GPIO pad config */ - pad_conf0 = config->pad_conf0; - if (config->is_gpio) - { - if (gpio >= bank->gpio_f1_range_start && - gpio <= bank->gpio_f1_range_end) - pad_conf0 |= PAD_FUNC1; - else - pad_conf0 |= PAD_FUNC0; - } - -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write Pad: Base(%p) - %x %x %x\n", - regmmio, pad_conf0, config->pad_conf1, config->pad_val); -#endif - - write32(regmmio + (PAD_CONF0_REG/sizeof(u32)), pad_conf0); - write32(regmmio + (PAD_CONF1_REG/sizeof(u32)), - config->pad_conf1); - write32(regmmio + (PAD_VAL_REG/sizeof(u32)), config->pad_val); - } - - if (bank->legacy_base != GP_LEGACY_BASE_NONE) - for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { - reg = bank->legacy_base + 0x20 * set; - -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, - "Write GPIO: Reg(%x) - %x %x %x %x %x\n", - reg, use_sel[set], io_sel[set], gp_lvl[set], - tpe[set], tne[set]); -#endif - - outl(use_sel[set], reg + LEGACY_USE_SEL_REG); - outl(io_sel[set], reg + LEGACY_IO_SEL_REG); - outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); - outl(tpe[set], reg + LEGACY_TPE_REG); - outl(tne[set], reg + LEGACY_TNE_REG); - - /* TS registers are WOC */ - outl(0, reg + LEGACY_TS_REG); - - if (bank->has_wake_en) - outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); - } -} - -static void setup_gpio_route(const struct soc_gpio_map *sus, - const struct soc_gpio_map *core) -{ - uint32_t route_reg = 0; - int i; - - /* FIXME: SCI interrupts should be routed regardlessy. */ - if (!CONFIG(HAVE_SMI_HANDLER)) - return; - - for (i = 0; i < 8; i++) { - /* SMI takes precedence and wake_en implies SCI. */ - if (sus[i].smi) { - route_reg |= ROUTE_SMI << (2 * i); - } else if (sus[i].sci) { - route_reg |= ROUTE_SCI << (2 * i); - } - - if (core[i].smi) { - route_reg |= ROUTE_SMI << (2 * (i + 8)); - } else if (core[i].sci) { - route_reg |= ROUTE_SCI << (2 * (i + 8)); - } - } - - smm_southcluster_save_gpio_route(route_reg); -} - -static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], - const struct gpio_bank *bank) -{ - u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET); - u32 val; - int i; - - /* Write all four DIRQ registers */ - for (i=0; i<4; ++i) { - val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | - dirq[i * 4 + 1] << 8 | dirq[i * 4]; - write32(reg + i, val); -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", - reg + i, val); -#endif - } -} - -void setup_soc_gpios(struct soc_gpio_config *config) -{ - if (config) { - setup_gpios(config->ncore, &gpncore_bank); - setup_gpios(config->score, &gpscore_bank); - setup_gpios(config->ssus, &gpssus_bank); - setup_gpio_route(config->ssus, config->score); - - if (config->core_dirq) - setup_dirqs(*config->core_dirq, &gpscore_bank); - if (config->sus_dirq) - setup_dirqs(*config->sus_dirq, &gpssus_bank); - } - -} - -struct soc_gpio_config* __weak mainboard_get_gpios(void) -{ - printk(BIOS_DEBUG, "Default/empty GPIO config\n"); - return NULL; -} - -/** \brief returns the input / output value from an SCORE GPIO - * - * @param gpio_num The GPIO number being read - * @return The current input or output value of the GPIO - */ -uint8_t read_score_gpio(uint8_t gpio_num) -{ - uint8_t retval = 0; - if (gpio_num < GPSCORE_COUNT) - retval = score_get_gpio(gpscore_gpio_to_pad[gpio_num]); - - return retval; -} - -/** \brief sets an output SCORE GPIO to desired value - * - * @param gpio_num The GPIO number being read - * @param val The value this output must be set to (0 or 1) - * @return void - */ -void write_score_gpio(uint8_t gpio_num, uint8_t val) -{ - if (gpio_num < GPSCORE_COUNT) - score_set_gpio(gpscore_gpio_to_pad[gpio_num], val); -} - -/** \brief returns the input / output value from an SSUS GPIO - * - * @param gpio_num The GPIO number being read - * @return The current input or output value of the GPIO - */ -uint8_t read_ssus_gpio(uint8_t gpio_num) -{ - uint8_t retval = 0; - if (gpio_num < GPSSUS_COUNT) - retval = ssus_get_gpio(gpssus_gpio_to_pad[gpio_num]); - - return retval; -} - -/** \brief sets an output SSUS GPIO to desired value - * - * @param gpio_num The GPIO number being read - * @param val The value this output must be set to (0 or 1) - * @return void - */ -void write_ssus_gpio(uint8_t gpio_num, uint8_t val) -{ - if (gpio_num < GPSSUS_COUNT) - ssus_set_gpio(gpssus_gpio_to_pad[gpio_num], val); -} - -/** \brief Sets up the function, pulls, and Input/Output of a Baytrail - * SSUS (S5) or SCORE (S0) GPIO - * - * @param ssus_gpio 1 if SSUS GPIO is being configured 0 if SCORE GPIO - * @param gpio_num The GPIO number being configured - * @param pconf0 function, pull direction, and pull value - * function: PAD_FUNC0 - PAD_FUNC7 - * pull assign: PAD_PULL_DISABLE / PAD_PULL_UP / PAD_PULL_DOWN - * pull_value: PAD_PU_2K / PAD_PU_10K / PAD_PU_20K / PAD_PU_40K - * @param pad_val input / output state and pad value - * io state: PAD_VAL_INPUT / PAD_VAL_OUTPUT - * pad value: PAD_VAL_HIGH / PAD_VAL_LOW - */ -static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num, - uint32_t pconf0, uint32_t pad_val) -{ - uint32_t reg; - uint32_t *pad_addr; - if (ssus_gpio) - pad_addr = ssus_pconf0(gpssus_gpio_to_pad[gpio_num]); - else - pad_addr = score_pconf0(gpscore_gpio_to_pad[gpio_num]); - - if ((ssus_gpio && gpio_num >= GPSSUS_COUNT) || - (gpio_num >= GPSCORE_COUNT)){ - printk(BIOS_WARNING,"Warning: Invalid %s GPIO specified (%d)\n", - ssus_gpio ? "SSUS" : "SCORE", gpio_num); - return; - } - - /* - * Pad Configuration 0 Register - * 2:0 - func_pin_mux - * 8:7 - Pull assignment: 00 - Non pull 01 - Pull Up 10 - Pull down - * 11 - reserved - * 10:9 - Pull strength: 00 - 2K 01 - 10K 10 - 20K 11 - 40K - */ - reg = PAD_CONFIG0_DEFAULT; - reg |= pconf0 & 0x787; - write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg); - - /* - * Pad Value Register - * 0: Pad value - * 1: output enable (0 is enabled) - * 2: input enable (0 is enabled) - */ - reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32))); - reg &= ~0x7; - reg |= pad_val & 0x7; - write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg); -} - -/** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO - * - */ -void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) -{ - configure_ssus_score_gpio(1, gpio_num, pconf0, pad_val); -} - -/** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO - * - */ -void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) -{ - configure_ssus_score_gpio(0, gpio_num, pconf0, pad_val); -} diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c deleted file mode 100644 index 37ce2d0b21..0000000000 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <drivers/i2c/designware/dw_i2c.h> -#include <soc/i2c.h> -#include <soc/iosf.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> - -#include "chip.h" - -/* Convert I2C bus number to PCI device and function */ -int dw_i2c_soc_bus_to_devfn(unsigned int bus) -{ - if (bus <= 6) - return PCI_DEVFN(SIO1_DEV, bus + 1); - else - return -1; -} - -/* Convert PCI device and function to I2C bus number */ -int dw_i2c_soc_dev_to_bus(struct device *dev) -{ - pci_devfn_t devfn = dev->path.pci.devfn; - if ((devfn >= SOC_DEVFN_I2C1) && (devfn <= SOC_DEVFN_I2C7)) - return PCI_FUNC(devfn) - 1; - else - return -1; -} - -/* Getting I2C bus configuration from devicetree config */ -const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) -{ - const struct soc_intel_fsp_baytrail_config *config; - const struct device *dev = pcidev_path_on_root(SOC_DEVFN_SOC); - - if (dev && dev->chip_info) { - config = dev->chip_info; - return &config->i2c[bus]; - } - - die("Could not find SA_DEV_ROOT devicetree config!\n"); -} - -#if !ENV_RAMSTAGE -static int lpss_i2c_early_init_bus(unsigned int bus) -{ - const struct dw_i2c_bus_config *config; - const struct device *tree_dev; - pci_devfn_t dev; - int devfn; - uintptr_t base; - - /* Find the PCI device for this bus controller */ - devfn = dw_i2c_soc_bus_to_devfn(bus); - if (devfn < 0) { - printk(BIOS_ERR, "I2C%u device not found\n", bus); - return -1; - } - - /* Look up the controller device in the devicetree */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = pcidev_path_on_root(devfn); - if (!tree_dev || !tree_dev->enabled) { - printk(BIOS_ERR, "I2C%u device not enabled\n", bus); - return -1; - } - - /* Skip if not enabled for early init */ - config = dw_i2c_get_soc_cfg(bus); - if (!config || !config->early_init) { - printk(BIOS_DEBUG, "I2C%u not enabled for early init\n", bus); - return -1; - } - - /* Prepare early base address for access before memory */ - base = EARLY_I2C_BASE(bus); - pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Take device out of reset */ - write32((void *)((uint32_t)base + I2C_SOFTWARE_RESET), I2C_RESET_APB | I2C_RESET_FUNC); - - /* Initialize the controller */ - if (dw_i2c_init(bus, config) < 0) { - printk(BIOS_ERR, "I2C%u failed to initialize\n", bus); - return -1; - } - - return 0; -} - -uintptr_t dw_i2c_base_address(unsigned int bus) -{ - int devfn; - pci_devfn_t dev; - uintptr_t base; - - /* Find device+function for this controller */ - devfn = dw_i2c_soc_bus_to_devfn(bus); - if (devfn < 0) - return 0; - - /* Form a PCI address for this device */ - dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - /* Read the first base address for this device */ - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; - - /* Attempt to initialize bus if base is not set yet */ - if (!base && !lpss_i2c_early_init_bus(bus)) - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; - return base; -} -#else - -uintptr_t dw_i2c_base_address(unsigned int bus) -{ - int devfn; - struct device *dev; - struct resource *bar = NULL; - - /* bus -> devfn */ - devfn = dw_i2c_soc_bus_to_devfn(bus); - - if (devfn < 0) - return (uintptr_t)NULL; - - /* devfn -> dev */ - dev = pcidev_path_on_root(devfn); - if (dev && dev->enabled) { - /* dev -> bar0 */ - bar = find_resource(dev, PCI_BASE_ADDRESS_0); - } - - if (bar) - return bar->base; - else - return (uintptr_t)NULL; -} - -static void i2c_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) -{ - struct resource *bar; - global_nvs_t *gnvs; - uint32_t val; - - /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); - return; - } - - /* Save BAR0 and BAR1 to ACPI NVS */ - bar = find_resource(dev, PCI_BASE_ADDRESS_0); - if (bar) - gnvs->dev.lpss_bar0[nvs_index] = (uint32_t)bar->base; - - bar = find_resource(dev, PCI_BASE_ADDRESS_1); - if (bar) - gnvs->dev.lpss_bar1[nvs_index] = (uint32_t)bar->base; - - /* Device is enabled in ACPI mode */ - gnvs->dev.lpss_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - val = iosf_lpss_read(iosf_reg); - val |= (LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN); - iosf_lpss_write(iosf_reg, val); - val = pci_read_config32(dev, PCI_COMMAND); - val |= PCI_COMMAND_INT_DISABLE; - pci_write_config32(dev, PCI_COMMAND, val); -} - -static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) -{ - uint32_t val; - - val = iosf_lpss_read(iosf_reg); - val &= ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP); - val |= (LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT); - iosf_lpss_write(iosf_reg, val); -} - -static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) -{ - int bus; - - bus = dw_i2c_soc_dev_to_bus(dev); - if (bus >= 0) { - *iosf_reg = LPSS_I2C1_CTL + (bus * 8); - *nvs_index = bus + 1; - } else { - - *iosf_reg = -1; - *nvs_index = -1; - } -} - -static void i2c_disable_resets(struct device *dev) -{ - uint32_t base; - - printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & 0xfffffff0; - write32((void *)(base + I2C_SOFTWARE_RESET), I2C_RESET_APB | I2C_RESET_FUNC); -} - -static void i2c_lpss_init(struct device *dev) -{ - struct soc_intel_fsp_baytrail_config *config = dev->chip_info; - int iosf_reg, nvs_index; - - dev_ctl_reg(dev, &iosf_reg, &nvs_index); - - if (iosf_reg < 0) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); - return; - } - dev_enable_snoop_and_pm(dev, iosf_reg); - i2c_disable_resets(dev); - - if (config && (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE)) - i2c_enable_acpi_mode(dev, iosf_reg, nvs_index); -} -/* - * This function ensures that the device is actually out of reset and - * it is ready for initialization sequence. - */ -static void dw_i2c_device_init(struct device *dev) -{ - int bus = dw_i2c_soc_dev_to_bus(dev); - - if (bus < 0) - return; - - if (!dw_i2c_base_address(bus)) - return; - i2c_lpss_init(dev); - dw_i2c_dev_init(dev); -} - -static struct device_operations i2c_dev_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_smbus, - .ops_i2c_bus = &dw_i2c_bus_ops, - .ops_pci = &pci_dev_ops_pci, - .init = dw_i2c_device_init, - .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, -}; - -static const unsigned short pci_device_ids[] = { - I2C1_DEVID, - I2C2_DEVID, - I2C3_DEVID, - I2C4_DEVID, - I2C5_DEVID, - I2C6_DEVID, - I2C7_DEVID, - 0 -}; - -static const struct pci_driver pch_i2c __pci_driver = { - .ops = &i2c_dev_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h deleted file mode 100644 index 917419e4df..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_ACPI_H_ -#define _BAYTRAIL_ACPI_H_ - -#include <arch/acpi.h> -#include <soc/nvs.h> -#include <device/device.h> - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); -void acpi_init_gnvs(global_nvs_t *gnvs); - -#ifndef __SIMPLE_DEVICE__ -unsigned long southcluster_write_acpi_tables(struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp); -void southcluster_inject_dsdt(struct device *device); -#endif - -#endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h deleted file mode 100644 index de902aac6f..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ -#define __SOC_INTEL_FSP_BAYTRAIL_BAYTRAIL_H__ - -#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS -#define CPU_MICROCODE_CBFS_LEN 0x26000 - -/* Southbridge internal device IO BARs (Set to match FSP settings) */ -#define SMBUS_IO_BASE 0xefa0 -#define SMBUS_SLAVE_ADDR 0x24 -#define DEFAULT_GPIOBASE 0x0500 -#define DEFAULT_ABASE 0x0400 - -/* Southbridge internal device MEM BARs (Set to match FSP settings) */ -#define DEFAULT_IBASE 0xfed08000 -#define DEFAULT_PBASE 0xfed03000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ -#define SKPAD 0xFC - -/* SOC types */ -#define SOC_TYPE_BAYTRAIL 0x0F1C - -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ -#include <device/device.h> - -int bridge_silicon_revision(void); -void rangeley_early_initialization(void); -void set_max_freq(void); - -/* soc.c */ -int soc_silicon_revision(void); -int soc_silicon_type(void); -int soc_silicon_supported(int type, int rev); -void soc_enable(struct device *dev); - -void report_platform_info(void); - -#endif /* __ASSEMBLER__ */ -#endif /* __ACPI__ */ - -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h deleted file mode 100644 index ec1e568bfd..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_DEVICE_NVS_H_ -#define _BAYTRAIL_DEVICE_NVS_H_ - -#include <stdint.h> - -#define LPSS_NVS_SIO_DMA1 0 -#define LPSS_NVS_I2C1 1 -#define LPSS_NVS_I2C2 2 -#define LPSS_NVS_I2C3 3 -#define LPSS_NVS_I2C4 4 -#define LPSS_NVS_I2C5 5 -#define LPSS_NVS_I2C6 6 -#define LPSS_NVS_I2C7 7 -#define LPSS_NVS_SIO_DMA2 8 -#define LPSS_NVS_SPI 9 -#define LPSS_NVS_PWM1 10 -#define LPSS_NVS_PWM2 11 -#define LPSS_NVS_HSUART1 12 -#define LPSS_NVS_HSUART2 13 - -#define SCC_NVS_MMC 0 -#define SCC_NVS_SDIO 1 -#define SCC_NVS_SD 2 - -typedef struct { - /* Device Enabled in ACPI Mode */ - u8 lpss_en[14]; - u8 scc_en[3]; - u8 lpe_en; - - /* BAR 0 */ - u32 lpss_bar0[14]; - u32 scc_bar0[3]; - u32 lpe_bar0; - - /* BAR 1 */ - u32 lpss_bar1[14]; - u32 scc_bar1[3]; - u32 lpe_bar1; - - /* Extra */ - u32 lpe_fw; /* LPE Firmware */ - u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ -} __packed device_nvs_t; - -#endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/ehci.h b/src/soc/intel/fsp_baytrail/include/soc/ehci.h deleted file mode 100644 index fe990b7017..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/ehci.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BAYTRAIL_EHCI_H -#define BAYTRAIL_EHCI_H - -/* EHCI PCI Registers */ -#define EHCI_CMD_STS 0x04 -# define INTRDIS (1 << 10) -#define EHCI_SBRN_FLA_PWC 0x60 -# define PORTWKIMP (1 << 16) -# define PORTWKCAPMASK (0x3ff << 17) -#define EHCI_USB2PDO 0x64 - -/* EHCI Memory Registers */ -#define USB2CMD 0x20 -# define USB2CMD_ASE (1 << 5) -# define USB2CMD_PSE (1 << 4) -# define USB2CMD_HCRESET (1 << 1) -# define USB2CMD_RS (1 << 0) -#define USB2STS 0x24 -# define USB2STS_HCHALT (1 << 12) - -/* RCBA EHCI Registers */ -#define RCBA_FUNC_DIS 0x220 -# define RCBA_EHCI_DIS (1 << 0) - -#endif /* BAYTRAIL_EHCI_H */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/gfx.h b/src/soc/intel/fsp_baytrail/include/soc/gfx.h deleted file mode 100644 index e7fc8ca604..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/gfx.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_GFX_H_ -#define _BAYTRAIL_GFX_H_ - -/* - * PCI config registers. - */ - -#define GGC 0x50 -# define GGC_VGA_DISABLE (1 << 1) -# define GGC_GTT_SIZE_MASK (3 << 8) -# define GGC_GTT_SIZE_0MB (0 << 8) -# define GGC_GTT_SIZE_1MB (1 << 8) -# define GGC_GTT_SIZE_2MB (2 << 8) -# define GGC_GSM_SIZE_MASK (0x1f << 3) -# define GGC_GSM_SIZE_0MB (0 << 3) -# define GGC_GSM_SIZE_32MB (1 << 3) -# define GGC_GSM_SIZE_64MB (2 << 3) -# define GGC_GSM_SIZE_128MB (4 << 3) - -#define GSM_BASE 0x5c -#define GTT_BASE 0x70 - -#define MSAC 0x62 -#define APERTURE_SIZE_MASK (3 << 1) -#define APERTURE_SIZE_128MB (0 << 1) -#define APERTURE_SIZE_256MB (1 << 1) -#define APERTURE_SIZE_512MB (3 << 1) - -#endif /* _BAYTRAIL_GFX_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h deleted file mode 100644 index 137ec95f14..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_GPIO_H_ -#define _BAYTRAIL_GPIO_H_ - -#include <stdint.h> -#include <device/mmio.h> -#include <soc/iomap.h> - -/* #define GPIO_DEBUG */ - -/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ -#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) -#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) -#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) - -/* DIRQ registers start at pad base + 0x980 */ -#define PAD_BASE_DIRQ_OFFSET 0x980 - -/* Pad register offset */ -#define PAD_CONF0_REG 0x0 -#define PAD_CONF1_REG 0x4 -#define PAD_VAL_REG 0x8 - -/* Legacy IO register base */ -#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) -#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) -/* Some banks have no legacy GPIO interface */ -#define GP_LEGACY_BASE_NONE 0xFFFF - -#define LEGACY_USE_SEL_REG 0x00 -#define LEGACY_IO_SEL_REG 0x04 -#define LEGACY_GP_LVL_REG 0x08 -#define LEGACY_TPE_REG 0x0C -#define LEGACY_TNE_REG 0x10 -#define LEGACY_TS_REG 0x14 -#define LEGACY_WAKE_EN_REG 0x18 - -/* Number of GPIOs in each bank */ -#define GPNCORE_COUNT 27 -#define GPSCORE_COUNT 102 -#define GPSSUS_COUNT 44 - -/* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_PEDGE_DISABLE 0 -#define GPIO_PEDGE_ENABLE 1 - -#define GPIO_NEDGE_DISABLE 0 -#define GPIO_NEDGE_ENABLE 1 - -/* config0[29] - Disable second mask */ -#define PAD_MASK2_DISABLE (1 << 29) - -/* config0[27] - Direct Irq En */ -#define PAD_IRQ_EN (1 << 27) - -/* config0[26] - gd_tne */ -#define PAD_TNE_IRQ (1 << 26) - -/* config0[25] - gd_tpe */ -#define PAD_TPE_IRQ (1 << 25) - -/* config0[24] - Gd Level */ -#define PAD_LEVEL_IRQ (1 << 24) -#define PAD_EDGE_IRQ (0 << 24) - -/* config0[17] - Slow clkgate / glitch filter */ -#define PAD_SLOWGF_ENABLE (1 << 17) - -/* config0[16] - Fast clkgate / glitch filter */ -#define PAD_FASTGF_ENABLE (1 << 16) - -/* config0[15] - Hysteresis enable (inverted) */ -#define PAD_HYST_DISABLE (1 << 15) -#define PAD_HYST_ENABLE (0 << 15) - -/* config0[14:13] - Hysteresis control */ -#define PAD_HYST_CTRL_DEFAULT (2 << 13) - -/* config0[11] - Bypass Flop */ -#define PAD_FLOP_BYPASS (1 << 11) -#define PAD_FLOP_ENABLE (0 << 11) - -/* config0[10:9] - Pull str */ -#define PAD_PU_2K (0 << 9) -#define PAD_PU_10K (1 << 9) -#define PAD_PU_20K (2 << 9) -#define PAD_PU_40K (3 << 9) - -/* config0[8:7] - Pull assign */ -#define PAD_PULL_DISABLE (0 << 7) -#define PAD_PULL_UP (1 << 7) -#define PAD_PULL_DOWN (2 << 7) - -/* config0[2:0] - Func. pin mux */ -#define PAD_FUNC0 0x0 -#define PAD_FUNC1 0x1 -#define PAD_FUNC2 0x2 -#define PAD_FUNC3 0x3 -#define PAD_FUNC4 0x4 -#define PAD_FUNC5 0x5 -#define PAD_FUNC6 0x6 - -/* pad config0 power-on values - We will not often want to change these */ -#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ - PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ - PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) - -/* pad config1 reg power-on values - Shouldn't need to change this */ -#define PAD_CONFIG1_DEFAULT 0x8000 - -/* pad_val[2] - Iinenb - active low */ -#define PAD_VAL_INPUT_DISABLE (1 << 2) -#define PAD_VAL_INPUT_ENABLE (0 << 2) - -/* pad_val[1] - Ioutenb - active low */ -#define PAD_VAL_OUTPUT_DISABLE (1 << 1) -#define PAD_VAL_OUTPUT_ENABLE (0 << 1) - -/* Input / Output state should usually be mutually exclusive */ -#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) -#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) - -/* pad_val[0] - Value */ -#define PAD_VAL_HIGH (1 << 0) -#define PAD_VAL_LOW (0 << 0) - -/* pad_val reg power-on default varies by pad, and apparently can cause issues - * if not set correctly, even if the pin isn't configured as GPIO. */ -#define PAD_VAL_DEFAULT PAD_VAL_INPUT - -/* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_LEGACY_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .is_gpio = 1 } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -#define GPIO_OUT_LOW_LEGACY \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH_LEGACY \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -#define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_MMIO, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_MMIO, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -/* Define no-pull / PU / PD configs for each functional config option */ -#define GPIO_FUNC(_func, _pudir, _str) \ - { .use_sel = GPIO_USE_MMIO, \ - .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ - PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -/* Default functional configs -- no PU */ -#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) -#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) -#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) -#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) -#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) -#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) -#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) - -/* ACPI GPIO routing. Assume everything is externally pulled and negative edge - * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ -#define GPIO_ACPI_SCI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .sci = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_WAKE \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_SMI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .smi = 1} - -/* End marker */ -#define GPIO_LIST_END 0xffffffff - -#define GPIO_END \ - { .pad_conf0 = GPIO_LIST_END } - -/* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU -#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_INPUT_PU_20K -#define GPIO_DEFAULT GPIO_FUNC0 - -/* 16 DirectIRQs per supported bank */ -#define GPIO_MAX_DIRQS 16 - -/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO - * function 1. Indicate first / last GPIOs with function 1. */ -#define GPIO_NONE 255 -/* All NCORE GPIOs are function 0 */ -#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE -#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE -/* SCORE GPIO [92:93] are function 1 */ -#define GPSCORE_GPIO_F1_RANGE_START 92 -#define GPSCORE_GPIO_F1_RANGE_END 93 -/* SSUS GPIO [11:21] are function 1 */ -#define GPSSUS_GPIO_F1_RANGE_START 11 -#define GPSSUS_GPIO_F1_RANGE_END 21 - -struct soc_gpio_map { - u32 pad_conf0; - u32 pad_conf1; - u32 pad_val; - u32 use_sel : 1; - u32 io_sel : 1; - u32 gp_lvl : 1; - u32 tpe : 1; - u32 tne : 1; - u32 wake_en : 1; - u32 smi : 1; - u32 is_gpio : 1; - u32 sci : 1; -} __packed; - -struct soc_gpio_config { - const struct soc_gpio_map *ncore; - const struct soc_gpio_map *score; - const struct soc_gpio_map *ssus; - const u8 (*core_dirq)[GPIO_MAX_DIRQS]; - const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; -}; - -/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ -struct gpio_bank { - const int gpio_count; - const u8 *gpio_to_pad; - const int legacy_base; - const unsigned long pad_base; - const u8 has_wake_en :1; - const u8 gpio_f1_range_start; - const u8 gpio_f1_range_end; -}; - -void smm_southcluster_save_gpio_route(uint32_t route); -void setup_soc_gpios(struct soc_gpio_config *config); -/* This function is weak and can be overridden by a mainboard function. */ -struct soc_gpio_config* mainboard_get_gpios(void); -uint8_t read_score_gpio(uint8_t gpio_num); -void write_score_gpio(uint8_t gpio_num, uint8_t val); -uint8_t read_ssus_gpio(uint8_t gpio_num); -void write_ssus_gpio(uint8_t gpio_num, uint8_t val); -void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); -void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); - -/* Functions / defines for changing GPIOs in romstage */ -/* SCORE Pad definitions. */ -#define UART_RXD_PAD 82 -#define UART_TXD_PAD 83 -#define PCU_SMB_CLK_PAD 88 -#define PCU_SMB_DATA_PAD 90 - -static inline uint32_t *score_pconf0(int pad_num) -{ - return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16); -} - -static inline uint32_t *ssus_pconf0(int pad_num) -{ - return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16); -} - -static inline void score_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = score_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - -static inline void ssus_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - - -/* These functions require that the input pad be configured as an input GPIO */ -static inline int score_get_gpio(int pad) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} - -static inline int ssus_get_gpio(int pad) -{ - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} - -/* These functions require that the output pad is configured as an output */ -/* GPIO and is mapped to memory space and not IO space. */ -static inline void score_set_gpio(int pad, int val) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - write32(val_addr, ((read32(val_addr) & ~0x1) | val)); -} - -static inline void ssus_set_gpio(int pad, int val) -{ - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - write32(val_addr, ((read32(val_addr) & ~0x1) | val)); -} - -static inline void ssus_disable_internal_pull(int pad) -{ - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~(0xf << 7); - write32(pconf0_addr, reg); -} - -#endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h deleted file mode 100644 index 3a4ff2c32b..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014-2019 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ -#define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ - -#define I2C_SOFTWARE_RESET 0x804 -#define I2C_RESET_APB (1 << 1) -#define I2C_RESET_FUNC (1 << 0) - -#endif /* __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/iomap.h b/src/soc/intel/fsp_baytrail/include/soc/iomap.h deleted file mode 100644 index d54d3fcc29..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/iomap.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IOMAP_H_ -#define _BAYTRAIL_IOMAP_H_ - -/* - * Memory Mapped IO bases. - */ - -/* PCI Configuration Space */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x10000000 - -/* Transactions in this range will abort */ -#define ABORT_BASE_ADDRESS 0xfeb00000 -#define ABORT_BASE_SIZE 0x00100000 - -/* Power Management Controller */ -#define PMC_BASE_ADDRESS 0xfed03000 -#define PMC_BASE_SIZE 0x400 - -/* IO Memory */ -#define IO_BASE_ADDRESS 0xfed0c000 -#define IO_BASE_OFFSET_GPSCORE 0x0000 -#define IO_BASE_OFFSET_GPNCORE 0x1000 -#define IO_BASE_OFFSET_GPSSUS 0x2000 -#define IO_BASE_SIZE 0x4000 - -/* Intel Legacy Block */ -#define ILB_BASE_ADDRESS 0xfed08000 -#define ILB_BASE_SIZE 0x400 - -/* SPI Bus */ -#define SPI_BASE_ADDRESS 0xfed01000 -#define SPI_BASE_SIZE 0x400 - -/* MODPHY */ -#define MPHY_BASE_ADDRESS 0xfef00000 -#define MPHY_BASE_SIZE 0x100000 - -/* Power Management Unit */ -#define PUNIT_BASE_ADDRESS 0xfed05000 -#define PUNIT_BASE_SIZE 0x800 - -/* Root Complex Base Address */ -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x400 - -/* High Performance Event Timer */ -#define HPET_BASE_ADDRESS 0xfed00000 -#define HPET_BASE_SIZE 0x400 - -/* Temporary Base Address */ -#define TEMP_BASE_ADDRESS 0xfd000000 -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -/* - * IO Port bases. - */ -#define ACPI_BASE_ADDRESS 0x0400 -#define ACPI_BASE_SIZE 0x80 - -#define GPIO_BASE_ADDRESS 0x0500 -#define GPIO_BASE_SIZE 0x100 - -#define SMBUS_BASE_ADDRESS 0xefa0 - -#ifndef __ACPI__ -#include <stdint.h> - -/* Read Top of Low Memory (BMBOUND) */ -uint32_t nc_read_top_of_low_memory(void); -#endif - -#endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h deleted file mode 100644 index 0982da68db..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IOSF_H_ -#define _BAYTRAIL_IOSF_H_ - -#include <stdint.h> -#include <soc/pci_devs.h> - -/* - * The Bay Trail SoC has a message network called IOSF Sideband. The access - * routines are through 3 registers in PCI config space of 00:00.0: - * MCR - control register - * MDR - data register - * MCRX - control register extension - * The extension register is only used for addresses that don't fit into the - * 8 bit register address. - */ - -#ifndef PCI_DEV -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) -#endif -#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) - -#define MCR_REG 0xd0 -#define IOSF_OPCODE(x) ((x) << 24) -#define IOSF_PORT(x) ((0xff & (x)) << 16) -#define IOSF_REG(x) ((0xff & (x)) << 8) -#define IOSF_REG_UPPER(x) (((~0xff) & (x))) -#define IOSF_BYTE_EN_0 0x10 -#define IOSF_BYTE_EN_1 0x20 -#define IOSF_BYTE_EN_2 0x40 -#define IOSF_BYTE_EN_3 0x80 -#define IOSF_BYTE_EN \ - (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) -#define MDR_REG 0xd4 -#define MCRX_REG 0xd8 - -uint32_t iosf_aunit_read(int reg); -void iosf_aunit_write(int reg, uint32_t val); -uint32_t iosf_cpu_bus_read(int reg); -void iosf_cpu_bus_write(int reg, uint32_t val); -uint32_t iosf_bunit_read(int reg); -void iosf_bunit_write(int reg, uint32_t val); -uint32_t iosf_dunit_read(int reg); -void iosf_dunit_write(int reg, uint32_t val); -/* Some registers are per channel while the globals live in dunit 0 */ -uint32_t iosf_dunit_ch0_read(int reg); -uint32_t iosf_dunit_ch1_read(int reg); -uint32_t iosf_punit_read(int reg); -void iosf_punit_write(int reg, uint32_t val); -uint32_t iosf_usbphy_read(int reg); -void iosf_usbphy_write(int reg, uint32_t val); -uint32_t iosf_ushphy_read(int reg); -void iosf_ushphy_write(int reg, uint32_t val); -uint32_t iosf_sec_read(int reg); -void iosf_sec_write(int reg, uint32_t val); -uint32_t iosf_port45_read(int reg); -void iosf_port45_write(int reg, uint32_t val); -uint32_t iosf_port46_read(int reg); -void iosf_port46_write(int reg, uint32_t val); -uint32_t iosf_port47_read(int reg); -void iosf_port47_write(int reg, uint32_t val); -uint32_t iosf_port55_read(int reg); -void iosf_port55_write(int reg, uint32_t val); -uint32_t iosf_port58_read(int reg); -void iosf_port58_write(int reg, uint32_t val); -uint32_t iosf_port59_read(int reg); -void iosf_port59_write(int reg, uint32_t val); -uint32_t iosf_port5a_read(int reg); -void iosf_port5a_write(int reg, uint32_t val); -uint32_t iosf_lpss_read(int reg); -void iosf_lpss_write(int reg, uint32_t val); -uint32_t iosf_ccu_read(int reg); -void iosf_ccu_write(int reg, uint32_t val); -uint32_t iosf_score_read(int reg); -void iosf_score_write(int reg, uint32_t val); -uint32_t iosf_scc_read(int reg); -void iosf_scc_write(int reg, uint32_t val); -uint32_t iosf_porta2_read(int reg); -void iosf_porta2_write(int reg, uint32_t val); -uint32_t iosf_ssus_read(int reg); -void iosf_ssus_write(int reg, uint32_t val); - -/* IOSF ports. */ -#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ -#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ -#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ -#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ -#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ -#define IOSF_PORT_PMC 0x04 /* Power Management Controller */ -#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ -#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ -#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ -#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ -#define IOSF_PORT_SEC 0x44 /* SEC */ -#define IOSF_PORT_0x45 0x45 -#define IOSF_PORT_0x46 0x46 -#define IOSF_PORT_0x47 0x47 -#define IOSF_PORT_SCORE 0x48 /* SCORE */ -#define IOSF_PORT_0x55 0x55 -#define IOSF_PORT_0x58 0x58 -#define IOSF_PORT_0x59 0x59 -#define IOSF_PORT_0x5a 0x5a -#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ -#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ -#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ -#define IOSF_PORT_0xa2 0xa2 -#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ -#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ -#define IOSF_PORT_SSUS 0xa8 /* SUS */ -#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ - -/* Read and write opcodes differ per port. */ -#define IOSF_OP_READ_AUNIT 0x10 -#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) -#define IOSF_OP_READ_SYSMEMC 0x10 -#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) -#define IOSF_OP_READ_CPU_BUS 0x10 -#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) -#define IOSF_OP_READ_BUNIT 0x10 -#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) -#define IOSF_OP_READ_PMC 0x06 -#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) -#define IOSF_OP_READ_GFX 0x00 -#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) -#define IOSF_OP_READ_SYSMEMIO 0x06 -#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) -#define IOSF_OP_READ_USBPHY 0x06 -#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) -#define IOSF_OP_READ_SEC 0x04 -#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) -#define IOSF_OP_READ_0x45 0x06 -#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) -#define IOSF_OP_READ_0x46 0x06 -#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) -#define IOSF_OP_READ_0x47 0x06 -#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) -#define IOSF_OP_READ_SCORE 0x06 -#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) -#define IOSF_OP_READ_0x55 0x04 -#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) -#define IOSF_OP_READ_0x58 0x06 -#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) -#define IOSF_OP_READ_0x59 0x06 -#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) -#define IOSF_OP_READ_0x5a 0x04 -#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) -#define IOSF_OP_READ_USHPHY 0x06 -#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) -#define IOSF_OP_READ_SCC 0x06 -#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) -#define IOSF_OP_READ_LPSS 0x06 -#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) -#define IOSF_OP_READ_0xa2 0x06 -#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) -#define IOSF_OP_READ_SATAPHY 0x00 -#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) -#define IOSF_OP_READ_PCIEPHY 0x00 -#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) -#define IOSF_OP_READ_SSUS 0x10 -#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) -#define IOSF_OP_READ_CCU 0x06 -#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) - -/* - * BUNIT Registers. - */ - -#define BNOCACHE 0x23 -/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ -#define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available RAM above 4GiB. It has a - * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 - * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB - * granularity care needs to be taken with the e820 map to account for a hole - * in the RAM. */ -#define BUNIT_BMBOUND_HI 0x26 -#define BUNIT_MMCONF_REG 0x27 -/* The SMMRR registers define the SMM region in MiB granularity. */ -#define BUNIT_SMRCP 0x2b -#define BUNIT_SMRRAC 0x2c -#define BUNIT_SMRWAC 0x2d -#define BUNIT_SMRRL 0x2e -#define BUNIT_SMRRH 0x2f -# define BUNIT_SMRR_ENABLE (1 << 31) - -/* SA ID bits. */ -#define SAI_IA_UNTRUSTED (1 << 0) -#define SAI_IA_SMM (1 << 2) -#define SAI_IA_BOOT (1 << 4) - -/* - * DUNIT Registers. - */ - -#define DRP 0x00 -# define DRP_DIMM0_RANK0_EN (0x01 << 0) -# define DRP_DIMM0_RANK1_EN (0x01 << 1) -# define DRP_DIMM1_RANK0_EN (0x01 << 2) -# define DRP_DIMM1_RANK1_EN (0x01 << 3) -# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ - DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) -#define DTR0 0x01 -# define DTR0_SPEED_MASK 0x03 -# define DTR0_SPEED_800 0x00 -# define DTR0_SPEED_1066 0x01 -# define DTR0_SPEED_1333 0x02 -# define DTR0_SPEED_1600 0x03 - -/* - * PUNIT Registers - */ -#define SB_BIOS_CONFIG 0x06 -# define SB_BIOS_CONFIG_ECC_EN (1 << 31) -# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) -# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) -# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) -# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) -# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) -# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) -# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) -# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) -# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) -# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) -# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) -#define BIOS_RESET_CPL 0x05 -# define BIOS_RESET_CPL_ALL_DONE (1 << 1) -# define BIOS_RESET_CPL_RESET_DONE (1 << 0) -#define PUNIT_PWRGT_CONTROL 0x60 -#define PUNIT_PWRGT_STATUS 0x61 -#define PUNIT_GPU_EC_VIRUS 0xd2 - -#define PUNIT_SOC_POWER_BUDGET 0x02 -#define PUNIT_SOC_ENERGY_CREDIT 0x03 -#define PUNIT_PTMC 0x80 -#define PUNIT_GFXT 0x88 -#define PUNIT_VEDT 0x89 -#define PUNIT_ISPT 0x8c -#define PUNIT_PTPS 0xb2 -#define PUNIT_TE_AUX0 0xb5 -#define PUNIT_TE_AUX1 0xb6 -#define PUNIT_TE_AUX2 0xb7 -#define PUNIT_TE_AUX3 0xb8 -#define PUNIT_TTE_VRIccMax 0xb9 -#define PUNIT_TTE_VRHot 0xba -#define PUNIT_TTE_XXPROCHOT 0xbb -#define PUNIT_TTE_SLM0 0xbc -#define PUNIT_TTE_SLM1 0xbd -#define PUNIT_TTE_SWT 0xbf - -/* - * LPSS Registers - */ -#define LPSS_SIO_DMA1_CTL 0x280 -#define LPSS_I2C1_CTL 0x288 -#define LPSS_I2C2_CTL 0x290 -#define LPSS_I2C3_CTL 0x298 -#define LPSS_I2C4_CTL 0x2a0 -#define LPSS_I2C5_CTL 0x2a8 -#define LPSS_I2C6_CTL 0x2b0 -#define LPSS_I2C7_CTL 0x2b8 -#define LPSS_SIO_DMA2_CTL 0x240 -#define LPSS_PWM1_CTL 0x248 -#define LPSS_PWM2_CTL 0x250 -#define LPSS_HSUART1_CTL 0x258 -#define LPSS_HSUART2_CTL 0x260 -#define LPSS_SPI_CTL 0x268 -# define LPSS_CTL_ACPI_INT_EN (1 << 21) -# define LPSS_CTL_PCI_CFG_DIS (1 << 20) -# define LPSS_CTL_SNOOP (1 << 18) -# define LPSS_CTL_NOSNOOP (1 << 19) -# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) - -/* - * SCC Registers - */ -#define SCC_SD_CTL 0x504 -#define SCC_SDIO_CTL 0x508 -#define SCC_MMC_CTL 0x50c -# define SCC_CTL_PCI_CFG_DIS (1 << 0) -# define SCC_CTL_ACPI_INT_EN (1 << 1) - -/* - * CCU Registers - */ - -#define PLT_CLK_CTRL_0 0x3c -#define PLT_CLK_CTRL_1 0x40 -#define PLT_CLK_CTRL_2 0x44 -#define PLT_CLK_CTRL_3 0x48 -#define PLT_CLK_CTRL_4 0x4c -#define PLT_CLK_CTRL_5 0x50 -# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) -# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) -# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) - -/* - * USBPHY Registers - */ -#define USBPHY_COMPBG 0x7f04 -#define USBPHY_PER_PORT_LANE0 0x4100 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 -#define USBPHY_PER_PORT_LANE1 0x4200 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 -#define USBPHY_PER_PORT_LANE2 0x4300 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 -#define USBPHY_PER_PORT_LANE3 0x4400 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 - -/* - * USHPHY Registers - */ -#define USHPHY_CDN_PLL_CONTROL 0x03c0 -#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 -#define USHPHY_CCDRLF 0x8040 -#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 -#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 -#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 -#define USHPHY_REE_DAC_CONTROL 0x80b8 -#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 - -/* - * LPE Registers - */ -#define LPE_PCICFGCTR1 0x0500 -# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) -# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) - -#endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/irq.h b/src/soc/intel/fsp_baytrail/include/soc/irq.h deleted file mode 100644 index de8fc03cde..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/irq.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_IRQ_H_ -#define _BAYTRAIL_IRQ_H_ - -#define PIRQA_APIC_IRQ 16 -#define PIRQB_APIC_IRQ 17 -#define PIRQC_APIC_IRQ 18 -#define PIRQD_APIC_IRQ 19 -#define PIRQE_APIC_IRQ 20 -#define PIRQF_APIC_IRQ 21 -#define PIRQG_APIC_IRQ 22 -#define PIRQH_APIC_IRQ 23 -/* The below IRQs are for when devices are in ACPI mode. Active low. */ -#define LPE_DMA0_IRQ 24 -#define LPE_DMA1_IRQ 25 -#define LPE_SSP0_IRQ 26 -#define LPE_SSP1_IRQ 27 -#define LPE_SSP2_IRQ 28 -#define LPE_IPC2HOST_IRQ 29 -#define LPSS_I2C1_IRQ 32 -#define LPSS_I2C2_IRQ 33 -#define LPSS_I2C3_IRQ 34 -#define LPSS_I2C4_IRQ 35 -#define LPSS_I2C5_IRQ 36 -#define LPSS_I2C6_IRQ 37 -#define LPSS_I2C7_IRQ 38 -#define LPSS_HSUART1_IRQ 39 -#define LPSS_HSUART2_IRQ 40 -#define LPSS_SPI_IRQ 41 -#define LPSS_DMA1_IRQ 42 -#define LPSS_DMA2_IRQ 43 -#define SCC_EMMC_IRQ 44 -#define SCC_SDIO_IRQ 46 -#define SCC_SD_IRQ 47 -#define GPIO_NC_IRQ 48 -#define GPIO_SC_IRQ 49 -#define GPIO_SUS_IRQ 50 -/* GPIO direct / dedicated IRQs. */ -#define GPIO_S0_DED_IRQ_0 51 -#define GPIO_S0_DED_IRQ_1 52 -#define GPIO_S0_DED_IRQ_2 53 -#define GPIO_S0_DED_IRQ_3 54 -#define GPIO_S0_DED_IRQ_4 55 -#define GPIO_S0_DED_IRQ_5 56 -#define GPIO_S0_DED_IRQ_6 57 -#define GPIO_S0_DED_IRQ_7 58 -#define GPIO_S0_DED_IRQ_8 59 -#define GPIO_S0_DED_IRQ_9 60 -#define GPIO_S0_DED_IRQ_10 61 -#define GPIO_S0_DED_IRQ_11 62 -#define GPIO_S0_DED_IRQ_12 63 -#define GPIO_S0_DED_IRQ_13 64 -#define GPIO_S0_DED_IRQ_14 65 -#define GPIO_S0_DED_IRQ_15 66 -#define GPIO_S5_DED_IRQ_0 67 -#define GPIO_S5_DED_IRQ_1 68 -#define GPIO_S5_DED_IRQ_2 69 -#define GPIO_S5_DED_IRQ_3 70 -#define GPIO_S5_DED_IRQ_4 71 -#define GPIO_S5_DED_IRQ_5 72 -#define GPIO_S5_DED_IRQ_6 73 -#define GPIO_S5_DED_IRQ_7 74 -#define GPIO_S5_DED_IRQ_8 75 -#define GPIO_S5_DED_IRQ_9 76 -#define GPIO_S5_DED_IRQ_10 77 -#define GPIO_S5_DED_IRQ_11 78 -#define GPIO_S5_DED_IRQ_12 79 -#define GPIO_S5_DED_IRQ_13 80 -#define GPIO_S5_DED_IRQ_14 81 -#define GPIO_S5_DED_IRQ_15 82 -/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ -#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot -#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot -#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) -#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) - -/* PIC IRQ settings. */ -#define PIRQ_PIC_IRQ3 0x3 -#define PIRQ_PIC_IRQ4 0x4 -#define PIRQ_PIC_IRQ5 0x5 -#define PIRQ_PIC_IRQ6 0x6 -#define PIRQ_PIC_IRQ7 0x7 -#define PIRQ_PIC_IRQ9 0x9 -#define PIRQ_PIC_IRQ10 0xa -#define PIRQ_PIC_IRQ11 0xb -#define PIRQ_PIC_IRQ12 0xc -#define PIRQ_PIC_IRQ14 0xe -#define PIRQ_PIC_IRQ15 0xf -#define PIRQ_PIC_IRQDISABLE 0x80 -#define PIRQ_PIC_UNKNOWN_UNUSED 0xff - -/* Overloaded term, but these values determine the per device route. */ -#define PIRQA 0 -#define PIRQB 1 -#define PIRQC 2 -#define PIRQD 3 -#define PIRQE 4 -#define PIRQF 5 -#define PIRQG 6 -#define PIRQH 7 - -/* These registers live behind the ILB_BASE_ADDRESS */ -#define ACTL 0x00 -# define SCIS_MASK 0x07 -# define SCIS_IRQ9 0x00 -# define SCIS_IRQ10 0x01 -# define SCIS_IRQ11 0x02 -# define SCIS_IRQ20 0x04 -# define SCIS_IRQ21 0x05 -# define SCIS_IRQ22 0x06 -# define SCIS_IRQ23 0x07 - -/* In each mainboard directory there should exist a header file irqroute.h that - * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) -#include <stdint.h> - -#define NUM_OF_PCI_DEVS 32 -#define NUM_PIRQS 8 - -struct baytrail_irq_route { - /* Per device configuration. */ - uint16_t pcidev[NUM_OF_PCI_DEVS]; - /* Route path for each internal PIRQx in PIC mode. */ - uint8_t pic[NUM_PIRQS]; -}; - -extern const struct baytrail_irq_route global_baytrail_irq_route; - -#define DEFINE_IRQ_ROUTES \ - const struct baytrail_irq_route global_baytrail_irq_route = { \ - .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ - .pic = { PIRQ_PIC_ROUTES, }, \ - } - -#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) - -#define PIRQ_PIC(pirq_, pic_irq_) \ - [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ - -/* used for ACPI only */ -#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h deleted file mode 100644 index defd34a2f5..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_LPC_H_ -#define _BAYTRAIL_LPC_H_ - -/* PCI config registers in LPC bridge. */ -#define REVID 0x08 -#define ABASE 0x40 /* IO BAR */ -#define PBASE 0x44 /* MEM BAR */ -#define GBASE 0x48 /* IO BAR */ -#define IOBASE 0x4c /* MEM BAR */ -#define IBASE 0x50 /* MEM BAR */ -#define SBASE 0x54 /* MEM BAR */ -#define MPBASE 0x58 /* MEM BAR */ -#define PUBASE 0x5c -#define SET_BAR_ENABLE 0x02 -#define UART_CONT 0x80 -#define RCBA 0xf0 -#define RCBA_ENABLE 0x01 - -#define ILB_ACTL 0 -#define ILB_MC 0x4 -#define ILB_PIRQA_ROUT 0x8 -#define ILB_PIRQB_ROUT 0x9 -#define ILB_PIRQC_ROUT 0xA -#define ILB_PIRQD_ROUT 0xB -#define ILB_PIRQE_ROUT 0xC -#define ILB_PIRQF_ROUT 0xD -#define ILB_PIRQG_ROUT 0xE -#define ILB_PIRQH_ROUT 0xF -#define ILB_SERIRQ_CNTL 0x10 -#define SCNT_CONTINUOUS_MODE (1 << 7) -#define SCNT_QUIET_MODE 0 -#define ILB_IR00 0x20 -#define ILB_IR01 0x22 -#define ILB_IR02 0x24 -#define ILB_IR03 0x26 -#define ILB_IR04 0x28 -#define ILB_IR05 0x2A -#define ILB_IR06 0x2C -#define ILB_IR07 0x2E -#define ILB_IR08 0x30 -#define ILB_IR09 0x32 -#define ILB_IR10 0x34 -#define ILB_IR11 0x36 -#define ILB_IR12 0x38 -#define ILB_IR13 0x3A -#define ILB_IR14 0x3C -#define ILB_IR15 0x3E -#define ILB_IR16 0x40 -#define ILB_IR17 0x42 -#define ILB_IR18 0x44 -#define ILB_IR19 0x46 -#define ILB_IR20 0x48 -#define ILB_IR21 0x4A -#define ILB_IR22 0x4C -#define ILB_IR23 0x4E -#define ILB_IR24 0x50 -#define ILB_IR25 0x52 -#define ILB_IR26 0x54 -#define ILB_IR27 0x56 -#define ILB_IR28 0x58 -#define ILB_IR29 0x5A -#define ILB_IR30 0x5C -#define ILB_IR31 0x5E -#define ILB_OIC 0x60 -#define SIRQEN (1 << 12) -#define AEN (1 << 8) - -#define RID_A_STEPPING_START 1 -#define RID_B_STEPPING_START 5 -#define RID_C_STEPPING_START 0xe -#define RID_D_STEPPING_START 0x11 - -enum baytrail_stepping { - STEP_A0, - STEP_A1, - STEP_B0, - STEP_B1, - STEP_B2, - STEP_B3, - STEP_C0, - STEP_D0, -}; - -/* Registers behind the RCBA_BASE_ADDRESS bar. */ -#define GCS 0x00 -# define BILD (1 << 0) - -/* Default IO range claimed by the LPC devices. The upper bound is exclusive. */ -#define LPC_DEFAULT_IO_RANGE_LOWER 0 -#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 -#define IO_APIC_RANGE_SIZE 0x1000 - -#endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h deleted file mode 100644 index 8edab59bdf..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_MSR_H_ -#define _BAYTRAIL_MSR_H_ - -#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_POWER_MISC 0x120 -#define MSR_POWER_CTL 0x1fc -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_LIMIT 0x610 -#define MSR_IACORE_RATIOS 0x66a -#define MSR_IACORE_TURBO_RATIOS 0x66c -#define MSR_IACORE_VIDS 0x66b -#define MSR_IACORE_TURBO_VIDS 0x66d - -/* Read BCLK from MSR */ -unsigned int bus_freq_khz(void); - -#endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h deleted file mode 100644 index df2fc60d71..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_NVS_H_ -#define _BAYTRAIL_NVS_H_ - -#include <soc/device_nvs.h> - -typedef struct { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ - u8 tpmp; /* 0x12 - TPM Present and Enabled */ - u8 tlvl; /* 0x13 - Throttle Level */ - u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ - u8 rsvd1[11]; - - /* Device Config */ - u8 s5u0; /* 0x20 - Enable USB0 in S5 */ - u8 s5u1; /* 0x21 - Enable USB1 in S5 */ - u8 s3u0; /* 0x22 - Enable USB0 in S3 */ - u8 s3u1; /* 0x23 - Enable USB1 in S3 */ - u8 tact; /* 0x24 - Thermal Active trip point */ - u8 tpsv; /* 0x25 - Thermal Passive trip point */ - u8 tcrt; /* 0x26 - Thermal Critical trip point */ - u8 dpte; /* 0x27 - Enable DPTF */ - u8 rsvd2[8]; - - /* Base Addresses */ - u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ - u32 tolm; /* 0x34 - Top of Low Memory */ - u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[196]; - - /* Pad 0x0100-0x0fff */ - u8 rsvd4[3840]; - - /* Baytrail LPSS (0x1000) */ - device_nvs_t dev; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); - -/* Used in SMM to find the ACPI GNVS address */ -global_nvs_t *smm_get_gnvs(void); - -#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h b/src/soc/intel/fsp_baytrail/include/soc/pattrs.h deleted file mode 100644 index 7b46345a47..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pattrs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PATTRS_H_ -#define _PATTRS_H_ - -#include <stdint.h> -#include <cpu/x86/msr.h> - -enum { - IACORE_MIN, - IACORE_LFM, - IACORE_MAX, - IACORE_TURBO, - IACORE_END -}; - -/* The pattrs structure is a common place to stash pertinent information - * about the processor or platform. Instead of going to the source (msrs, cpuid) - * every time an attribute is needed use the pattrs structure. - */ -struct pattrs { - msr_t platform_id; - msr_t platform_info; - int iacore_ratios[IACORE_END]; - int iacore_vids[IACORE_END]; - uint32_t cpuid; - int revid; - int stepping; - const void *microcode_patch; - int address_bits; - int num_cpus; - unsigned int bclk_khz; -}; - -/* This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - -static inline const struct pattrs *pattrs_get(void) -{ - return &PATTRS_GLOB_NAME; -} - - -#endif /* _PATTRS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h deleted file mode 100644 index 5e5b8071df..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PCI_DEVS_H_ -#define _BAYTRAIL_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -/* All these devices live on bus 0 with the associated device and function */ - -/* SoC transaction router */ -#define SOC_DEV 0x0 -#define SOC_FUNC 0 -# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) - - -/* Graphics and Display */ -#define GFX_DEV 0x2 -#define GFX_FUNC 0 -# define SOC_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) - -/* MIPI */ -#define MIPI_DEV 0x3 -#define MIPI_FUNC 0 -# define SOC_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) - - -/* SDIO Port */ -#define EMMC_DEV 0x10 -#define EMMC_FUNC 0 -# define SOC_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) - -/* SDIO Port */ -#define SDIO_DEV 0x11 -#define SDIO_FUNC 0 -# define SOC_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) - -/* SD Port */ -#define SD_DEV 0x12 -#define SD_FUNC 0 -# define SOC_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) - -/* SATA */ -#define SATA_DEV 0x13 -#define SATA_FUNC 0 -# define SOC_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) - -/* xHCI */ -#define XHCI_DEV 0x14 -#define XHCI_FUNC 0 -# define XHCI_FUS_REG 0xE0 -# define XHCI_FUNC_DISABLE (1 << 0) -# define XHCI_USB2PR_REG 0xD0 -# define SOC_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) - -/* LPE Audio */ -#define LPE_DEV 0x15 -#define LPE_FUNC 0 -# define SOC_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) - -/* OTG */ -#define OTG_DEV 0x16 -#define OTG_FUNC 0 -# define SOC_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) - -/* MMC Port */ -#define MMC45_DEV 0x17 -#define MMC45_FUNC 0 -# define SOC_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) - -/* Serial IO 1 */ -#define SIO1_DEV 0x18 -# define SIO_DMA1_DEV SIO1_DEV -# define SIO_DMA1_FUNC 0 -# define I2C1_DEV SIO1_DEV -# define I2C1_FUNC 1 -# define I2C2_DEV SIO1_DEV -# define I2C2_FUNC 2 -# define I2C3_DEV SIO1_DEV -# define I2C3_FUNC 3 -# define I2C4_DEV SIO1_DEV -# define I2C4_FUNC 4 -# define I2C5_DEV SIO1_DEV -# define I2C5_FUNC 5 -# define I2C6_DEV SIO1_DEV -# define I2C6_FUNC 6 -# define I2C7_DEV SIO1_DEV -# define I2C7_FUNC 7 -# define SOC_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define SOC_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define SOC_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define SOC_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define SOC_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define SOC_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define SOC_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define SOC_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) - -#define PCH_DEV_SLOT_I2C1 I2C1_DEV - -/* Trusted Execution Engine */ -#define TXE_DEV 0x1a -#define TXE_FUNC 0 -# define SOC_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) - -/* HD Audio */ -#define HDA_DEV 0x1b -#define HDA_FUNC 0 -# define SOC_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) - -/* PCIe Ports */ -#define PCIE_DEV 0x1c -# define PCIE_PORT1_DEV PCIE_DEV -# define PCIE_PORT1_FUNC 0 -# define PCIE_PORT2_DEV PCIE_DEV -# define PCIE_PORT2_FUNC 1 -# define PCIE_PORT3_DEV PCIE_DEV -# define PCIE_PORT3_FUNC 2 -# define PCIE_PORT4_DEV PCIE_DEV -# define PCIE_PORT4_FUNC 3 -# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) - -/* EHCI */ -#define EHCI_DEV 0x1d -#define EHCI_FUNC 0 -# define SOC_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) - -/* Serial IO 2 */ -#define SIO2_DEV 0x1e -# define SIO_DMA2_DEV SIO2_DEV -# define SIO_DMA2_FUNC 0 -# define PWM1_DEV SIO2_DEV -# define PWM1_FUNC 1 -# define PWM2_DEV SIO2_DEV -# define PWM2_FUNC 2 -# define HSUART1_DEV SIO2_DEV -# define HSUART1_FUNC 3 -# define HSUART2_DEV SIO2_DEV -# define HSUART2_FUNC 4 -# define SPI_DEV SIO2_DEV -# define SPI_FUNC 5 -# define SOC_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define SOC_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define SOC_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define SOC_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define SOC_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SOC_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) - - -/* Platform Controller Unit */ -#define PCU_DEV 0x1f -# define LPC_DEV PCU_DEV -# define LPC_FUNC 0 -# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) - -# define SMBUS_DEV PCU_DEV -# define SMBUS_FUNC 3 -# define SOC_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) - -#define SOC_DEVID 0x0f00 -#define GFX_DEVID 0x0f31 -#define MIPI_DEVID 0x0f38 -#define EMMC_DEVID 0x0f14 -#define SDIO_DEVID 0x0f15 -#define SD_DEVID 0x0f16 -#define IDE1_DEVID 0x0f20 -#define IDE2_DEVID 0x0f21 -#define AHCI1_DEVID 0x0f22 -#define AHCI2_DEVID 0x0f23 -#define XHCI_DEVID 0x0f35 -#define LPE_DEVID 0x0f28 -#define OTG_DEVID 0x0f37 -#define MMC45_DEVID 0x0f50 -#define SIO_DMA1_DEVID 0x0f40 -#define I2C1_DEVID 0x0f41 -#define I2C2_DEVID 0x0f42 -#define I2C3_DEVID 0x0f43 -#define I2C4_DEVID 0x0f44 -#define I2C5_DEVID 0x0f45 -#define I2C6_DEVID 0x0f46 -#define I2C7_DEVID 0x0f47 -#define TXE_DEVID 0x0f18 -#define HDA_DEVID 0x0f04 -#define PCIE_PORT1_DEVID 0x0f48 -#define PCIE_PORT2_DEVID 0x0f4a -#define PCIE_PORT3_DEVID 0x0f4c -#define PCIE_PORT4_DEVID 0x0f4e -#define EHCI_DEVID 0x0f34 -#define SIO_DMA2_DEVID 0x0f06 -#define PWM1_DEVID 0x0f08 -#define PWM2_DEVID 0x0f09 -#define HSUART1_DEVID 0x0f0a -#define HSUART2_DEVID 0x0f0c -#define SPI_DEVID 0xf0e -#define LPC_DEVID 0x0f1c -#define SMBUS_DEVID 0x0f12 - -#endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pcie.h b/src/soc/intel/fsp_baytrail/include/soc/pcie.h deleted file mode 100644 index 9d2d3de53e..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pcie.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PCIE_H_ -#define _BAYTRAIL_PCIE_H_ - -/* PCIe root port config space registers. */ -#define XCAP 0x40 -# define SI (1 << 24) -#define DCAP 0x44 -# define MPS_MASK 0x7 -#define DCTL_DSTS 0x48 -# define URE (1 << 3) -# define FEE (1 << 2) -# define NFE (1 << 1) -# define CEE (1 << 0) -#define LCAP 0x4c -# define L1EXIT_SHIFT 15 -# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT) -#define LCTL 0x50 -# define CCC (1 << 6) -# define RL (1 << 5) -# define LD (1 << 4) -#define LSTS 0x52 -#define SLCAP 0x54 -# define SLN_SHIFT 19 -# define SLS_SHIFT 15 -# define SLV_SHIFT 7 -# define HPC (1 << 6) -# define HPS (1 << 5) -#define SLCTL_SLSTS 0x58 -# define PDS (1 << 22) -#define DCAP2 0x64 -# define OBFFS (0x3 << 18) -# define LTRMS (1 << 11) -#define DSTS2 0x68 -# define OBFFEN (3 << 13) -# define LTRME (1 << 10) -# define CTD (1 << 4) -#define CHCFG 0xd0 -# define UPSD (1 << 24) -# define UNRS (1 << 15) -# define UPRS (1 << 14) -#define MPC2 0xd4 -# define IPF (1 << 11) -# define LSTP (1 << 6) -# define EOIFD (1 << 1) -#define MPC 0xd8 -# define CCEL_SHIFT 15 -# define CCEL_MASK (0x7 << CCEL_SHIFT) -#define RPPGEN 0xe0 -# define RPSCGEN (1 << 15) -# define LCLKREQEN (1 << 13) -# define BBCLKREQEN (1 << 12) -# define SRDLCGEN (1 << 11) -# define SRDBCGEN (1 << 10) -# define RPDLCGEN (1 << 9) -# define RPDBCGEN (1 << 8) -#define PWRCTL 0xe8 -# define RPL1SQPOL (1 << 1) -# define RPDTSQPOL (1 << 0) -#define PHYCTL2_IOSFBCTL 0xf4 -# define PLL_OFF_EN (1 << 8) -# define TDFT (3 << 14) -# define TXCFGCHWAIT (3 << 12) -# define SIID (3 << 26) -#define STRPFUSECFG 0xfc -# define LANECFG_SHIFT 14 -# define LANECFG_MASK (0x3 << LANECFG_SHIFT) -#define AERCH 0x100 -#define NFTS 0x314 -#define L0SC 0x318 -#define CFG2 0x320 -# define CSREN (1 << 22) -# define LATGC_SHIFT 6 -# define LATGC_MASK (0x7 << LATGC_SHIFT) -#define PCIEDBG 0x324 -# define SPCE (1 << 5) -#define PCIESTS1 0x328 -#define PCIEALC 0x338 -#define RTP 0x33c -#define PHYCTL4 0x408 -# define SQDIS (1 << 27) - - -#endif /* _BAYTRAIL_PCIE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h deleted file mode 100644 index 9e588addae..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_PMC_H_ -#define _BAYTRAIL_PMC_H_ - -#include <arch/acpi.h> - -#define IOCOM1 0x3f8 - -/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ -#define PRSTS 0x00 -# define PMC_WDT_STS (1 << 15) -# define SEC_GBLRST_STS (1 << 7) -# define SEC_WDT_STS (1 << 6) -# define WOL_OVR_WK_STS (1 << 5) -# define PMC_WAKE_STS (1 << 4) -#define PMC_CFG 0x08 -# define SPS (1 << 5) -# define NO_REBOOT (1 << 4) -# define SX_ENT_TO_EN (1 << 3) -# define TIMING_T581_SHIFT (0) -# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) -# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) -# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) -# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) -# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) -#define VLV_PM_STS 0x0c -# define PMC_MSG_FULL_STS (1 << 24) -# define PMC_MSG_4_FULL_STS (1 << 23) -# define PMC_MSG_3_FULL_STS (1 << 22) -# define PMC_MSG_2_FULL_STS (1 << 21) -# define PMC_MSG_1_FULL_STS (1 << 20) -# define CODE_REQ (1 << 8) -# define HPR_ENT_TO (1 << 2) -# define SX_ENT_TO (1 << 1) -#define GEN_PMCON1 0x20 -# define UART_EN (1 << 24) -# define DISB (1 << 23) -# define MEM_SR (1 << 21) -# define SRS (1 << 20) -# define CTS (1 << 19) -# define MS4V (1 << 18) -# define PWR_FLR (1 << 16) -# define PME_B0_S5_DIS (1 << 15) -# define SUS_PWR_FLR (1 << 14) -# define WOL_EN_OVRD (1 << 13) -# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) -# define GEN_RST_STS (1 << 9) -# define RPS (1 << 2) -# define AFTERG3_EN (1 << 0) -#define GEN_PMCON2 0x24 -# define SLPSX_STR_POL_LOCK (1 << 18) -# define BIOS_PCI_EXP_EN (1 << 10) -# define PWRBTN_LVL (1 << 9) -# define SMI_LOCK (1 << 4) -#define ETR 0x48 -# define CF9LOCK (1 << 31) -# define LTR_DEF (1 << 22) -# define IGNORE_HPET (1 << 21) -# define CF9GR (1 << 20) -# define CWORWRE (1 << 18) -#define FUNC_DIS 0x34 -# define SIO_DMA2_DIS (1 << 0) -# define PWM1_DIS (1 << 1) -# define PWM2_DIS (1 << 2) -# define HSUART1_DIS (1 << 3) -# define HSUART2_DIS (1 << 4) -# define SPI_DIS (1 << 5) -# define SDIO_DIS (1 << 9) -# define SD_DIS (1 << 10) -# define MMC_DIS (1 << 11) -# define HDA_DIS (1 << 12) -# define LPE_DIS (1 << 13) -# define OTG_DIS (1 << 14) -# define XHCI_DIS (1 << 15) -# define SATA_DIS (1 << 17) -# define EHCI_DIS (1 << 18) -# define TXE_DIS (1 << 19) -# define PCIE_PORT1_DIS (1 << 20) -# define PCIE_PORT2_DIS (1 << 21) -# define PCIE_PORT3_DIS (1 << 22) -# define PCIE_PORT4_DIS (1 << 23) -# define SIO_DMA1_DIS (1 << 24) -# define I2C1_DIS (1 << 25) -# define I2C2_DIS (1 << 26) -# define I2C3_DIS (1 << 27) -# define I2C4_DIS (1 << 28) -# define I2C5_DIS (1 << 29) -# define I2C6_DIS (1 << 30) -# define I2C7_DIS (1 << 31) -#define FUNC_DIS2 0x38 -# define USH_SS_PHY_DIS (1 << 2) -# define OTG_SS_PHY_DIS (1 << 1) -# define SMBUS_DIS (1 << 0) -#define GPIO_ROUT 0x58 -# define ROUTE_MASK 3 -# define ROUTE_NONE 0 -# define ROUTE_SMI 1 -# define ROUTE_SCI 2 -#define PLT_CLK_CTL_0 0x60 -#define PLT_CLK_CTL_1 0x64 -#define PLT_CLK_CTL_2 0x68 -#define PLT_CLK_CTL_3 0x6c -#define PLT_CLK_CTL_4 0x70 -#define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) -# define CLK_CTL_D3_LPE (0x0 << 0) -# define CLK_CTL_ON (0x1 << 0) -# define CLK_CTL_OFF (0x2 << 0) -#define PME_STS 0xc0 -#define GPE_LEVEL_EDGE 0xc4 -# define GPE_EDGE 0 -# define GPE_LEVEL 1 -#define GPE_POLARITY 0xc8 -# define GPE_ACTIVE_HIGH 1 -# define GPE_ACTIVE_LOW 0 -#define LOCK 0xcc - -/* IO Mapped registers behind ACPI_BASE_ADDRESS */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define USB_STS (1 << 13) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define USB_WAKE_EN (1 << 13) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define GPE0_STS 0x20 -#define CORE_GPIO_STS7 (1 << 31) -#define CORE_GPIO_STS6 (1 << 30) -#define CORE_GPIO_STS5 (1 << 29) -#define CORE_GPIO_STS4 (1 << 28) -#define CORE_GPIO_STS3 (1 << 27) -#define CORE_GPIO_STS2 (1 << 26) -#define CORE_GPIO_STS1 (1 << 25) -#define CORE_GPIO_STS0 (1 << 24) -#define SUS_GPIO_STS7 (1 << 23) -#define SUS_GPIO_STS6 (1 << 22) -#define SUS_GPIO_STS5 (1 << 21) -#define SUS_GPIO_STS4 (1 << 20) -#define SUS_GPIO_STS3 (1 << 19) -#define SUS_GPIO_STS2 (1 << 18) -#define SUS_GPIO_STS1 (1 << 17) -#define SUS_GPIO_STS0 (1 << 16) -#define PME_B0_STS_BIT 13 -#define PME_B0_STS (1 << PME_B0_STS_BIT) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define PCIE_WAKE3_STS (1 << 8) -#define PCIE_WAKE2_STS (1 << 7) -#define PCIE_WAKE1_STS (1 << 6) -#define GUNIT_SCI_STS (1 << 5) -#define PUNIT_SCI_STS (1 << 4) -#define PCIE_WAKE0_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define CORE_GPIO_EN7 (1 << 31) -#define CORE_GPIO_EN6 (1 << 30) -#define CORE_GPIO_EN5 (1 << 29) -#define CORE_GPIO_EN4 (1 << 28) -#define CORE_GPIO_EN3 (1 << 27) -#define CORE_GPIO_EN2 (1 << 26) -#define CORE_GPIO_EN1 (1 << 25) -#define CORE_GPIO_EN0 (1 << 24) -#define SUS_GPIO_EN7_BIT 23 -#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) -#define SUS_GPIO_EN6_BIT 22 -#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) -#define SUS_GPIO_EN5_BIT 21 -#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) -#define SUS_GPIO_EN4_BIT 20 -#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) -#define SUS_GPIO_EN3_BIT 19 -#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) -#define SUS_GPIO_EN2_BIT 18 -#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) -#define SUS_GPIO_EN1_BIT 17 -#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) -#define SUS_GPIO_EN0_BIT 16 -#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) -#define PME_B0_EN (1 << 13) -#define BATLOW_EN (1 << 10) -#define PCI_EXP_EN (1 << 9) -#define PCIE_WAKE3_EN (1 << 8) -#define PCIE_WAKE2_EN (1 << 7) -#define PCIE_WAKE1_EN (1 << 6) -#define PCIE_WAKE0_EN (1 << 3) -#define SWGPE_EN (1 << 2) -#define HOT_PLUG_EN (1 << 1) -#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT -#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) -#define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define USB_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GPIO_SMI 0x38 -#define UPRWC 0x3c -# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable -#define GPE_CTRL 0x40 -#define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) -# define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -# define TCO_LOCK (1 << 12) -# define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 - -/* I/O ports */ -#define RST_CNT 0xcf9 -# define FULL_RST (1 << 3) -# define RST_CPU (1 << 2) -# define SYS_RST (1 << 1) - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -/* Track power state from reset to log events. */ -struct chipset_power_state { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t pm1_cnt; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint32_t tco_sts; - uint32_t prsts; - uint32_t gen_pmcon1; - uint32_t gen_pmcon2; -} __packed; - -/* Power Management Utility Functions. */ -uint16_t get_pmbase(void); -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); -uint32_t clear_alt_status(void); -void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); - -uint32_t chipset_prev_sleep_state(uint32_t clear); - -void southcluster_log_state(void); - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h deleted file mode 100644 index 45fda9e937..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_RAMSTAGE_H_ -#define _BAYTRAIL_RAMSTAGE_H_ - -#include <device/device.h> - -/* The baytrail_init_pre_device() function is called prior to device - * initialization, but it's after console and cbmem has been reinitialized. */ -void baytrail_init_pre_device(void); -void baytrail_init_cpus(struct device *dev); -void southcluster_enable_dev(struct device *dev); -void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); - -extern struct pci_operations soc_pci_ops; - -#endif /* _BAYTRAIL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h deleted file mode 100644 index dce953993a..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_ROMSTAGE_H_ -#define _BAYTRAIL_ROMSTAGE_H_ - -#include <stdint.h> -#include <drivers/intel/fsp1_0/fsp_util.h> - -void main(FSP_INFO_HEADER *fsp_info_header); - -#define NUM_ROMSTAGE_TS 4 - -void tco_disable(void); -void punit_init(void); -void early_mainboard_romstage_entry(void); -void late_mainboard_romstage_entry(void); -void get_func_disables(uint32_t *mask, uint32_t *mask2); -void byt_config_com1_and_enable(void); - -#endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/smm.h b/src/soc/intel/fsp_baytrail/include/soc/smm.h deleted file mode 100644 index b6e24a8a0f..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/smm.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_SMM_H_ -#define _BAYTRAIL_SMM_H_ - - -#endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/spi.h b/src/soc/intel/fsp_baytrail/include/soc/spi.h deleted file mode 100644 index 1ac0b59e56..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/spi.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_SPI_H_ -#define _BAYTRAIL_SPI_H_ - -#include <stdint.h> - -/* These registers live behind SPI_BASE_ADDRESS. */ -#define HSFSTS 0x04 -# define FLOCKDN (0x1 << 15) -#define PREOP 0x94 -#define OPTYPE 0x96 -#define OPMENU0 0x98 -#define OPMENU1 0x9c -#define LVSCC 0xc4 -# define VCL (0x1 << 23) -# define EO(x) (((x) & 0xff) << 8) -# define WG_1_BYTE (0x0 << 2) -# define WG_64_BYTE (0x1 << 2) -# define BES_256_BYTE (0x0 << 0) -# define BES_4_KB (0x1 << 0) -# define BES_8_KB (0x2 << 0) -# define BES_64_KB (0x3 << 0) -#define UVSCC 0xc8 -#define SCS 0xf8 -# define SMIWPEN (0x1 << 7) -#define BCR 0xfc -# define EISS (0x1 << 5) -# define SRC_MASK (0x3 << 2) -# define SRC_CACHE_NO_PREFETCH (0x0 << 2) -# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2) -# define SRC_CACHE_PREFETCH (0x2 << 2) -# define BCR_LE (0x1 << 1) -# define BCR_WPD (0x1 << 0) - -/* - * SPI lockdown configuration. - */ -struct spi_config { - uint16_t preop; - uint16_t optype; - uint32_t opmenu[2]; - uint32_t lvscc; - uint32_t uvscc; -}; - -/* Return 0 on success < 0 on failure. */ -int mainboard_get_spi_config(struct spi_config *cfg); - -#endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/xhci.h b/src/soc/intel/fsp_baytrail/include/soc/xhci.h deleted file mode 100644 index d509b51a6a..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/xhci.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef BAYTRAIL_XHCI_H -#define BAYTRAIL_XHCI_H - -/* XHCI PCI Registers */ -#define XHCI_PWR_CTL_STS 0x74 -#define XHCI_USB2PR 0xd0 -#define XHCI_USB2PRM 0xd4 -#define XHCI_USB3PR 0xd8 -#define XHCI_USB3PRM 0xdc -#define XHCI_USB2PDO 0xe4 -#define XHCI_USB3PDO 0xe8 - -/* XHCI Memory Registers */ -#define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10)) -# define XHCI_USB3_PORTSC_CHST (0x7f << 17) -# define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -# define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ -# define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ -# define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ -# define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -# define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -# define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ -# define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ -# define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ -# define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ -# define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */ - -/* The Fuse register is incorrect for Baytrail-M so use hardcoded values */ -#define BYTM_USB2_PORT_COUNT 4 -#define BYTM_USB2_PORT_MAP 0xf -#define BYTM_USB3_PORT_COUNT 1 -#define BYTM_USB3_PORT_MAP 0x1 - -#define XHCI_RESET_TIMEOUT 100000 /* 100ms */ - -#endif /* BAYTRAIL_XHCI_H */ diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c deleted file mode 100644 index 25f82ababd..0000000000 --- a/src/soc/intel/fsp_baytrail/iosf.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <soc/iosf.h> - -static inline void write_iosf_reg(int reg, uint32_t value) -{ - pci_s_write_config32(IOSF_PCI_DEV, reg, value); -} - -static inline uint32_t read_iosf_reg(int reg) -{ - return pci_s_read_config32(IOSF_PCI_DEV, reg); -} - -/* Common sequences for all the port accesses. */ -static uint32_t iosf_read_port(uint32_t cr, int reg) -{ - cr |= IOSF_REG(reg) | IOSF_BYTE_EN; - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); -} - -static void iosf_write_port(uint32_t cr, int reg, uint32_t val) -{ - cr |= IOSF_REG(reg) | IOSF_BYTE_EN; - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); -} - -#define IOSF_READ(port) \ - IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) -#define IOSF_WRITE(port) \ - IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) - -uint32_t iosf_bunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(BUNIT), reg); -} - -void iosf_bunit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(BUNIT), reg, val); -} - -uint32_t iosf_dunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(SYSMEMC), reg); -} - -uint32_t iosf_dunit_ch0_read(int reg) -{ - return iosf_dunit_read(reg); -} - -uint32_t iosf_dunit_ch1_read(int reg) -{ - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_DUNIT_CH1); - return iosf_read_port(cr, reg); -} - -void iosf_dunit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); -} - -uint32_t iosf_punit_read(int reg) -{ - return iosf_read_port(IOSF_READ(PMC), reg); -} - -void iosf_punit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(PMC), reg, val); -} - -uint32_t iosf_usbphy_read(int reg) -{ - return iosf_read_port(IOSF_READ(USBPHY), reg); -} - -void iosf_usbphy_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); -} - -uint32_t iosf_ushphy_read(int reg) -{ - return iosf_read_port(IOSF_READ(USHPHY), reg); -} - -void iosf_ushphy_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); -} - -uint32_t iosf_lpss_read(int reg) -{ - return iosf_read_port(IOSF_READ(LPSS), reg); -} - -void iosf_lpss_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(LPSS), reg, val); -} - -uint32_t iosf_ccu_read(int reg) -{ - return iosf_read_port(IOSF_READ(CCU), reg); -} - -void iosf_ccu_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CCU), reg, val); -} - -uint32_t iosf_score_read(int reg) -{ - return iosf_read_port(IOSF_READ(SCORE), reg); -} - -void iosf_score_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SCORE), reg, val); -} - -uint32_t iosf_scc_read(int reg) -{ - return iosf_read_port(IOSF_READ(SCC), reg); -} - -void iosf_scc_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SCC), reg, val); -} - -uint32_t iosf_aunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(AUNIT), reg); -} - -void iosf_aunit_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); -} - -uint32_t iosf_cpu_bus_read(int reg) -{ - return iosf_read_port(IOSF_READ(CPU_BUS), reg); -} - -void iosf_cpu_bus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); -} - -uint32_t iosf_sec_read(int reg) -{ - return iosf_read_port(IOSF_READ(SEC), reg); -} - -void iosf_sec_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SEC), reg, val); -} - -uint32_t iosf_port45_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x45), reg); -} - -void iosf_port45_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x45), reg, val); -} - -uint32_t iosf_port46_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x46), reg); -} - -void iosf_port46_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x46), reg, val); -} - -uint32_t iosf_port47_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x47), reg); -} - -void iosf_port47_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x47), reg, val); -} - -uint32_t iosf_port55_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x55), reg); -} - -void iosf_port55_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x55), reg, val); -} - -uint32_t iosf_port58_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x58), reg); -} - -void iosf_port58_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x58), reg, val); -} - -uint32_t iosf_port59_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x59), reg); -} - -void iosf_port59_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x59), reg, val); -} - -uint32_t iosf_port5a_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x5a), reg); -} - -void iosf_port5a_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x5a), reg, val); -} - -uint32_t iosf_porta2_read(int reg) -{ - return iosf_read_port(IOSF_READ(0xa2), reg); -} - -void iosf_porta2_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0xa2), reg, val); -} - -uint32_t iosf_ssus_read(int reg) -{ - return iosf_read_port(IOSF_READ(SSUS), reg); -} - -void iosf_ssus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SSUS), reg, val); -} diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c deleted file mode 100644 index 91f8880a18..0000000000 --- a/src/soc/intel/fsp_baytrail/lpe.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <cbmem.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <reg_script.h> - -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/pattrs.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/ramstage.h> -#include "chip.h" - - -/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB - * address. Just take 1MiB @ 512MiB. */ -#define FIRMWARE_PHYS_BASE (512 << 20) -#define FIRMWARE_PHYS_LENGTH (1 << 20) -#define FIRMWARE_PCI_REG_BASE 0xa8 -#define FIRMWARE_PCI_REG_LENGTH 0xac -#define FIRMWARE_REG_BASE_C0 0x144000 -#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) - -static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index) -{ - struct resource *res; - - res = find_resource(dev, index); - if (res) - *field = res->base; -} - -static void lpe_enable_acpi_mode(struct device *dev) -{ - static const struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, - LPE_PCICFGCTR1_PCI_CFG_DIS | - LPE_PCICFGCTR1_ACPI_INT_EN), - REG_SCRIPT_END - }; - global_nvs_t *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); - return; - } - - /* Save BAR0, BAR1, and firmware base to ACPI NVS */ - assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); - assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); - - /* Device is enabled in ACPI mode */ - gnvs->dev.lpe_en = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); -} - -static void setup_codec_clock(struct device *dev) -{ - uint32_t reg; - u32 *clk_reg; - struct soc_intel_fsp_baytrail_config *config; - const char *freq_str; - - config = config_of(dev); - switch (config->lpe_codec_clk_freq) { - case 19: - freq_str = "19.2"; - reg = CLK_FREQ_19P2MHZ; - break; - case 25: - freq_str = "25"; - reg = CLK_FREQ_25MHZ; - break; - default: - printk(BIOS_DEBUG, "LPE codec clock not required.\n"); - return; - } - - /* Default to always running. */ - reg |= CLK_CTL_ON; - - if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { - printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); - return; - } - - printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); - - clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); - clk_reg += config->lpe_codec_clk_num; - - write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); -} - -static void lpe_stash_firmware_info(struct device *dev) -{ - struct resource *res; - struct resource *mmio; - const struct pattrs *pattrs = pattrs_get(); - - res = find_resource(dev, FIRMWARE_PCI_REG_BASE); - if (res == NULL) { - printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); - return; - } - - /* Continue using old way of informing firmware address / size. */ - pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); - pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); - - /* C0 and later steppings use an offset in the MMIO space. */ - if (pattrs->stepping >= STEP_C0) { - mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), - res->base); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), - res->size); - } -} - -static void lpe_init(struct device *dev) -{ - struct soc_intel_fsp_baytrail_config *config = config_of(dev); - - lpe_stash_firmware_info(dev); - - setup_codec_clock(dev); - - if (config->LpeAcpiModeEnable == LPE_ACPI_MODE_ENABLED) - lpe_enable_acpi_mode(dev); -} - -static void lpe_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - - reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, - FIRMWARE_PHYS_BASE >> 10, - FIRMWARE_PHYS_LENGTH >> 10); -} - -static const struct device_operations device_ops = { - .read_resources = lpe_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpe_init, - .enable = NULL, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = LPE_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c deleted file mode 100644 index 2ad6fb3804..0000000000 --- a/src/soc/intel/fsp_baytrail/lpss.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cbmem.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <reg_script.h> - -#include <soc/iosf.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> - -#include "chip.h" - -static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) -{ - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, - LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; - struct resource *bar; - global_nvs_t *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_ERR, "Unable to locate Global NVS\n"); - return; - } - - /* Save BAR0 and BAR1 to ACPI NVS */ - bar = find_resource(dev, PCI_BASE_ADDRESS_0); - if (bar) - gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; - - bar = find_resource(dev, PCI_BASE_ADDRESS_1); - if (bar) - gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; - - /* Device is enabled in ACPI mode */ - gnvs->dev.lpss_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); -} - -static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) -{ - struct reg_script ops[] = { - REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, - ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), - LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), - REG_SCRIPT_END, - }; - - reg_script_run_on_dev(dev, ops); -} - -static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) -{ - *iosf_reg = -1; - *nvs_index = -1; -#define SET_IOSF_REG(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - *iosf_reg = LPSS_ ## name_ ## _CTL; \ - *nvs_index = LPSS_NVS_ ## name_ - - switch (dev->path.pci.devfn) { - SET_IOSF_REG(SIO_DMA1); - break; - SET_IOSF_REG(SIO_DMA2); - break; - SET_IOSF_REG(PWM1); - break; - SET_IOSF_REG(PWM2); - break; - SET_IOSF_REG(HSUART1); - break; - SET_IOSF_REG(HSUART2); - break; - SET_IOSF_REG(SPI); - break; - } -} - -static void lpss_init(struct device *dev) -{ - struct soc_intel_fsp_baytrail_config *config = config_of(dev); - int iosf_reg, nvs_index; - - dev_ctl_reg(dev, &iosf_reg, &nvs_index); - - if (iosf_reg < 0) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); - return; - } - dev_enable_snoop_and_pm(dev, iosf_reg); - - if (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE) - dev_enable_acpi_mode(dev, iosf_reg, nvs_index); -} - -static struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpss_init, - .enable = NULL, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - SIO_DMA1_DEVID, - SIO_DMA2_DEVID, - PWM1_DEVID, - PWM2_DEVID, - HSUART1_DEVID, - HSUART2_DEVID, - SPI_DEVID, - 0, -}; - -static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c deleted file mode 100644 index d8dcf49acb..0000000000 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <cpu/x86/smm.h> -#include <soc/iosf.h> -#include <drivers/intel/fsp1_0/fsp_util.h> -#include <types.h> - -static uintptr_t smm_region_start(void) -{ - return (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; -} - -static size_t smm_region_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - -/** @brief get the top of usable low memory from the FSP's HOB list - * - * The FSP's reserved memory sits just below the SMM region. The memory - * region below it is usable memory. - * - * The entire memory map is shown in northcluster.c - * - * @return pointer to the first byte of reserved memory - */ - -void *cbmem_top_chipset(void) -{ - return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); -} - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = smm_region_start(); - *size = smm_region_size(); -} diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c deleted file mode 100644 index 474ba84890..0000000000 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/x86/lapic.h> -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> -#include <cbmem.h> -#include <soc/baytrail.h> -#include <drivers/intel/fsp1_0/fsp_util.h> -#include <arch/acpi.h> - -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - -/* Host Memory Map: - * - * +--------------------------+ BMBOUND_HI - * | Usable DRAM | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ BMBOUND - * | TPM | - * +--------------------------+ IMR2 - * | TXE | - * +--------------------------+ IMR1 - * | iGD | - * +--------------------------+ - * | GTT | - * +--------------------------+ SMMRRH, IRM0 - * | TSEG | - * +--------------------------+ SMMRRL - * | FSP | - * +--------------------------+ SMMRRL - 2MB - * | Usable DRAM | - * +--------------------------+ FFFFF - * | ROM Area | - * +--------------------------+ A0000 - * | Usable DRAM | - * +--------------------------+ 0 - * - * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resource model: - * - * +--------------------------+ BMBOUND_HI - * | Cacheable/Usable | - * +--------------------------+ 4GiB - * - * +--------------------------+ BMBOUND - * | Uncacheable/Reserved | - * +--------------------------+ SMMRRH - * | Cacheable/Reserved | - * +--------------------------+ SMMRRL - 2MB - * | Cacheable/Usable | - * +--------------------------+ 0 - */ - -/* - * Get the top of low memory for use by ACPI - */ -uint32_t nc_read_top_of_low_memory(void) -{ - uint32_t fsp_mem_base = 0; - GetLowMemorySize(&fsp_mem_base); - - return fsp_mem_base; -} - -static int get_pcie_bar(u32 *base) -{ - u32 pciexbar_reg; - - *base = 0; - - pciexbar_reg = iosf_bunit_read(BUNIT_MMCONF_REG); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); - return 256; - -} - -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - - resource = new_resource(dev, index++); /* Local APIC */ - resource->base = LAPIC_DEFAULT_BASE; - resource->size = 0x00001000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); -} - -static void mc_add_dram_resources(struct device *dev) -{ - u32 bmbound, bsmmrrl; - int index = 0; - uint64_t highmem_size = 0; - uint32_t fsp_mem_base = 0; - - GetHighMemorySize(&highmem_size); - fsp_mem_base=(uint32_t)cbmem_top(); - - bmbound = iosf_bunit_read(BUNIT_BMBOUND); - bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; - - if (bsmmrrl){ - printk(BIOS_DEBUG, "UMA, GTT & SMM memory location: 0x%x\n" - "UMA, GTT & SMM memory size: %dM\n", - bsmmrrl, (bmbound - bsmmrrl) >> 20); - - printk(BIOS_DEBUG, "FSP memory location: 0x%x\nFSP memory size: %dM\n", - fsp_mem_base, (bsmmrrl - fsp_mem_base) >> 20); - } - - printk(BIOS_INFO, "Available memory below 4GB: 0x%08x (%dM)\n", - fsp_mem_base, fsp_mem_base >> 20); - - /* Report the memory regions. */ - ram_resource(dev, index++, 0, legacy_hole_base_k); - ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, - ((fsp_mem_base >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); - - /* Mark SMM & FSP regions reserved */ - mmio_resource(dev, index++, fsp_mem_base >> 10, - (bmbound - fsp_mem_base) >> 10); - - if (highmem_size) { - ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); - } - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - highmem_size >> 20); - - add_fixed_resources(dev, index); -} - -static void nc_read_resources(struct device *dev) -{ - u32 pcie_config_base; - int buses; - - /* Call the normal read_resources */ - pci_dev_read_resources(dev); - - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - buses = get_pcie_bar(&pcie_config_base); - if (buses) { - struct resource *resource = new_resource(dev, 0xcf); - mmconf_resource_init(resource, pcie_config_base, buses); - } - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); -} - -static void nc_enable(struct device *dev) -{ - print_fsp_info(); -} - -static struct device_operations nc_ops = { - .read_resources = nc_read_resources, - .acpi_fill_ssdt_generator = generate_cpu_entries, - .set_resources = DEVICE_NOOP, - .enable_resources = NULL, - .init = NULL, - .enable = &nc_enable, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver nc_driver __pci_driver = { - .ops = &nc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = SOC_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/placeholders.c b/src/soc/intel/fsp_baytrail/placeholders.c deleted file mode 100644 index e9a8757557..0000000000 --- a/src/soc/intel/fsp_baytrail/placeholders.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <device/pci_rom.h> -#include <soc/acpi.h> - - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} - -/* Rmodules don't like weak symbols. */ -u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c deleted file mode 100644 index 10838e3a99..0000000000 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <cbmem.h> -#include <console/console.h> - -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <security/vboot/vbnv.h> - -#if defined(__SIMPLE_DEVICE__) - -static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); - -static inline pci_devfn_t get_pcu_dev(void) -{ - return pcu_dev; -} - -#else /* !__SIMPLE_DEVICE__ */ -#include <device/device.h> -#include <device/pci.h> - -static struct device *pcu_dev; -static struct device *get_pcu_dev(void) -{ - if (pcu_dev == NULL) - pcu_dev = pcidev_on_root(PCU_DEV, 0); - return pcu_dev; -} -#endif - -uint16_t get_pmbase(void) -{ - return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; -} - -static void print_num_status_bits(int num_bits, uint32_t status, - const char *bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static void print_status_bits(uint32_t status, const char *bit_names[]) -{ - print_num_status_bits(32, status, bit_names); -} - -static uint32_t print_smi_status(uint32_t smi_sts) -{ - static const char *smi_sts_bits[] = { - [2] = "BIOS", - [4] = "SLP_SMI", - [5] = "APM", - [6] = "SWSMI_TMR", - [8] = "PM1", - [9] = "GPE0", - [12] = "DEVMON", - [13] = "TCO", - [14] = "PERIODIC", - [15] = "ILB", - [16] = "SMBUS_SMI", - [17] = "LEGACY_USB2", - [18] = "INTEL_USB2", - [20] = "PCI_EXP_SMI", - [26] = "SPI", - [28] = "PUNIT", - [29] = "GUNIT", - }; - - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_status_bits(smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; -} - -static uint32_t reset_smi_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl(pmbase + SMI_STS); - outl(smi_sts, pmbase + SMI_STS); - return smi_sts; -} - -uint32_t clear_smi_status(void) -{ - return print_smi_status(reset_smi_status()); -} - -void enable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en |= mask; - outl(smi_en, pmbase + SMI_EN); -} - -void disable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); - smi_en &= ~mask; - outl(smi_en, pmbase + SMI_EN); -} - -void enable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= mask; - outl(pm1_cnt, pmbase + PM1_CNT); -} - -void disable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt &= ~mask; - outl(pm1_cnt, pmbase + PM1_CNT); -} - -static uint16_t reset_pm1_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw(pmbase + PM1_STS); - outw(pm1_sts, pmbase + PM1_STS); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char *pm1_sts_bits[] = { - [0] = "TMROF", - [5] = "GBL", - [8] = "PWRBTN", - [10] = "RTC", - [11] = "PRBTNOR", - [13] = "USB", - [14] = "PCIEXPWAK", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_status_bits(pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -uint16_t clear_pm1_status(void) -{ - return print_pm1_status(reset_pm1_status()); -} - -void enable_pm1(uint16_t events) -{ - outw(events, get_pmbase() + PM1_EN); -} - -static uint32_t print_tco_status(uint32_t tco_sts) -{ - static const char *tco_sts_bits[] = { - [3] = "TIMEOUT", - [17] = "SECOND_TO", - }; - - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_status_bits(tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; -} - -static uint32_t reset_tco_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t tco_sts = inl(pmbase + TCO_STS); - uint32_t tco_en = inl(pmbase + TCO1_CNT); - - outl(tco_sts, pmbase + TCO_STS); - return tco_sts & tco_en; -} - -uint32_t clear_tco_status(void) -{ - return print_tco_status(reset_tco_status()); -} - -void enable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en |= mask; - outl(gpe0_en, pmbase + GPE0_EN); -} - -void disable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); - gpe0_en &= ~mask; - outl(gpe0_en, pmbase + GPE0_EN); -} - -void disable_all_gpe(void) -{ - disable_gpe(~0); -} - - -static uint32_t reset_gpe_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl(pmbase + GPE0_STS); - outl(gpe_sts, pmbase + GPE0_STS); - return gpe_sts; -} - -static uint32_t print_gpe_sts(uint32_t gpe_sts) -{ - static const char *gpe_sts_bits[] = { - [1] = "HOTPLUG", - [2] = "SWGPE", - [3] = "PCIE_WAKE0", - [4] = "PUNIT", - [5] = "GUNIT", - [6] = "PCIE_WAKE1", - [7] = "PCIE_WAKE2", - [8] = "PCIE_WAKE3", - [9] = "PCI_EXP", - [10] = "BATLOW", - [13] = "PME_B0", - [16] = "SUS_GPIO_0", - [17] = "SUS_GPIO_1", - [18] = "SUS_GPIO_2", - [19] = "SUS_GPIO_3", - [20] = "SUS_GPIO_4", - [21] = "SUS_GPIO_5", - [22] = "SUS_GPIO_6", - [23] = "SUS_GPIO_7", - [24] = "CORE_GPIO_0", - [25] = "CORE_GPIO_1", - [26] = "CORE_GPIO_2", - [27] = "CORE_GPIO_3", - [28] = "CORE_GPIO_4", - [29] = "CORE_GPIO_5", - [30] = "CORE_GPIO_6", - [31] = "CORE_GPIO_7", - }; - - if (!gpe_sts) - return gpe_sts; - - printk(BIOS_DEBUG, "GPE0a_STS: "); - print_status_bits(gpe_sts, gpe_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return gpe_sts; -} - -uint32_t clear_gpe_status(void) -{ - return print_gpe_sts(reset_gpe_status()); -} - -static uint32_t reset_alt_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); - outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); - return alt_gpio_smi; -} - -static uint32_t print_alt_sts(uint32_t alt_gpio_smi) -{ - uint32_t alt_gpio_sts; - static const char *alt_gpio_smi_sts_bits[] = { - [0] = "SUS_GPIO_0", - [1] = "SUS_GPIO_1", - [2] = "SUS_GPIO_2", - [3] = "SUS_GPIO_3", - [4] = "SUS_GPIO_4", - [5] = "SUS_GPIO_5", - [6] = "SUS_GPIO_6", - [7] = "SUS_GPIO_7", - [8] = "CORE_GPIO_0", - [9] = "CORE_GPIO_1", - [10] = "CORE_GPIO_2", - [11] = "CORE_GPIO_3", - [12] = "CORE_GPIO_4", - [13] = "CORE_GPIO_5", - [14] = "CORE_GPIO_6", - [15] = "CORE_GPIO_7", - }; - - /* Status bits are in the upper 16 bits. */ - alt_gpio_sts = alt_gpio_smi >> 16; - if (!alt_gpio_sts) - return alt_gpio_smi; - - printk(BIOS_DEBUG, "ALT_GPIO_SMI: "); - print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return alt_gpio_smi; -} - -uint32_t clear_alt_status(void) -{ - return print_alt_sts(reset_alt_status()); -} - -void clear_pmc_status(void) -{ - uint32_t prsts; - uint32_t gen_pmcon1; - - prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - - /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); - write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); -} - -int vbnv_cmos_failed(void) -{ - uint32_t gen_pmcon1; - int rtc_fail; - struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - - if (ps != NULL) - gen_pmcon1 = ps->gen_pmcon1; - else - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - - rtc_fail = !!(gen_pmcon1 & RPS); - - if (rtc_fail) - printk(BIOS_DEBUG, "RTC failure.\n"); - - return rtc_fail; -} diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c deleted file mode 100644 index 754c5f5c45..0000000000 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cr.h> -#include <cpu/x86/msr.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <stdlib.h> -#include <string.h> - -#include <soc/gpio.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/msr.h> -#include <soc/pattrs.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> - -/* Global PATTRS */ -DEFINE_PATTRS; - -#define SHOW_PATTRS 1 - -static void detect_num_cpus(struct pattrs *attrs) -{ - int ecx = 0; - - while (1) { - struct cpuid_result leaf_b; - - leaf_b = cpuid_ext(0xb, ecx); - - /* Bay Trail doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2). */ - if ((leaf_b.ecx & 0xff00) == 0x0200) { - attrs->num_cpus = leaf_b.ebx & 0xffff; - break; - } - ecx++; - } -} - -static inline void fill_in_msr(msr_t *msr, int idx) -{ - *msr = rdmsr(idx); - if (SHOW_PATTRS) { - printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", - idx, msr->hi, msr->lo); - } -} - -static const char *stepping_str[] = { - "A0", "A1", "B0", "B1", "B2", "B3", "C0", "D0", -}; - -static void fill_in_pattrs(void) -{ - struct device *dev; - msr_t msr; - struct pattrs *attrs = (struct pattrs *)pattrs_get(); - - attrs->cpuid = cpuid_eax(1); - dev = pcidev_on_root(LPC_DEV, LPC_FUNC); - attrs->revid = pci_read_config8(dev, REVID); - /* The revision to stepping IDs have two values per metal stepping. */ - if (attrs->revid >= RID_D_STEPPING_START) { - attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; - attrs->stepping += STEP_D0; - } else if (attrs->revid >= RID_C_STEPPING_START) { - attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; - attrs->stepping += STEP_C0; - } else if (attrs->revid >= RID_B_STEPPING_START) { - attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; - attrs->stepping += STEP_B0; - } else { - attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; - attrs->stepping += STEP_A0; - } - - attrs->microcode_patch = intel_microcode_find(); - attrs->address_bits = cpuid_eax(0x80000008) & 0xff; - detect_num_cpus(attrs); - - if (SHOW_PATTRS) { - printk(BIOS_DEBUG, - "CPUID: %08x\nCores: %d\nRevision ID: %02x\nStepping: %s\n", - attrs->cpuid, attrs->num_cpus, attrs->revid, - (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : - stepping_str[attrs->stepping]); - } - - fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); - fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); - - /* Set IA core speed ratio and voltages */ - msr = rdmsr(MSR_IACORE_RATIOS); - attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; - attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_RATIOS); - attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ - - msr = rdmsr(MSR_IACORE_VIDS); - attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; - attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_VIDS); - attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ - - /* Set bus clock speed */ - attrs->bclk_khz = bus_freq_khz(); -} - -static void s3_resume_prepare(void) -{ - global_nvs_t *gnvs; - - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (gnvs == NULL) - return; - - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(global_nvs_t)); -} - -void baytrail_init_pre_device(void) -{ - struct soc_gpio_config *config; - - fill_in_pattrs(); - - /* Allow for SSE instructions to be executed. */ - write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); - - /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); - - /* Get GPIO initial states from mainboard */ - config = mainboard_get_gpios(); - setup_soc_gpios(config); -} diff --git a/src/soc/intel/fsp_baytrail/romstage/Makefile.inc b/src/soc/intel/fsp_baytrail/romstage/Makefile.inc deleted file mode 100644 index c47dfb5c16..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Google Inc. -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -romstage-y += romstage.c -romstage-y += pmc.c -romstage-y += report_platform.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/fsp_baytrail/romstage/pmc.c b/src/soc/intel/fsp_baytrail/romstage/pmc.c deleted file mode 100644 index dab31bf314..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/pmc.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stddef.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/romstage.h> -#include "../chip.h" - -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c deleted file mode 100644 index 2b5dad7ab7..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/pci_ops.h> -#include <soc/iosf.h> -#include <soc/baytrail.h> -#include <cpu/x86/msr.h> -#include <soc/msr.h> -#include <cpu/x86/name.h> - -static void print_dram_info(void) -{ - const int mrc_ver_reg = 0xf0; - const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); - uint32_t reg; - int num_channels; - int speed; - uint32_t ch0; - uint32_t ch1; - - reg = pci_read_config32(soc_dev, mrc_ver_reg); - - printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); - - /* Number of channels enabled and DDR3 type. Determine number of - * channels by the keying of the rank enable bits [3:0]. * */ - ch0 = iosf_dunit_ch0_read(DRP); - ch1 = iosf_dunit_ch1_read(DRP); - num_channels = 0; - if (ch0 & DRP_RANK_MASK) - num_channels++; - if (ch1 & DRP_RANK_MASK) - num_channels++; - - printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, - (reg & (1 << 22)) ? "LP" : ""); - - /* DRAM frequency -- all channels run at same frequency. */ - reg = iosf_dunit_read(DTR0); - switch (reg & 0x3) { - case 0: - speed = 800; break; - case 1: - speed = 1066; break; - case 2: - speed = 1333; break; - case 3: - speed = 1600; break; - } - printk(BIOS_INFO, "%dMHz\n", speed); -} - -#define VARIANT_ID_BYTE 18 -#define VARIANT_ID_MASK 7 -void report_platform_info(void) -{ - const char *baytrail_variants[4] = { - "Bay Trail-I (ISG/embedded)", - "Bay Trail-T (Tablet)", - "Bay Trail-D (Desktop)", - "Bay Trail-M (Mobile)", - }; - msr_t platform_id = rdmsr(IA32_PLATFORM_ID); - uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK; - - printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ? - baytrail_variants[variant] : "Unknown"); - print_dram_info(); - -} diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c deleted file mode 100644 index f347591599..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stddef.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <arch/cbfs.h> -#include <arch/early_variables.h> -#include <console/console.h> -#include <console/usb.h> -#include <cbmem.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <program_loading.h> -#include <romstage_handoff.h> -#include <timestamp.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/acpi.h> -#include <soc/baytrail.h> -#include <drivers/intel/fsp1_0/fsp_util.h> -#include <soc/pmc.h> -#include <soc/spi.h> -#include <version.h> -#include <pc80/mc146818rtc.h> -#include <device/pci_def.h> -#include <security/vboot/vboot_common.h> - -/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ -uint32_t chipset_prev_sleep_state(uint32_t clear) -{ - /* Default to S0. */ - uint32_t prev_sleep_state = ACPI_S0; - uint32_t pm1_sts; - uint32_t pm1_cnt; - uint32_t gen_pmcon1; - - /* Read Power State */ - pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - - printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", - pm1_sts, pm1_cnt, gen_pmcon1); - - if (pm1_sts & WAK_STS) { - switch (acpi_sleep_from_pm1(pm1_cnt)) { - case ACPI_S3: - if (CONFIG(HAVE_ACPI_RESUME)) - prev_sleep_state = ACPI_S3; - break; - case ACPI_S4: - prev_sleep_state = ACPI_S4; - break; - - case ACPI_S5: - prev_sleep_state = ACPI_S5; - break; - } - /* If set Clear SLP_TYP. */ - if (clear == 1) { - outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); - } - } - - if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { - prev_sleep_state = ACPI_S5; - } - - return prev_sleep_state; -} - -static void program_base_addresses(void) -{ - uint32_t reg; - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, PBASE, reg); - reg = IO_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, IOBASE, reg); - reg = ILB_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, IBASE, reg); - reg = SPI_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, SBASE, reg); - reg = MPHY_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | RCBA_ENABLE; - pci_write_config32(LPC_BDF, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, ABASE, reg); - reg = GPIO_BASE_ADDRESS | SET_BAR_ENABLE; - pci_write_config32(LPC_BDF, GBASE, reg); -} - -static void spi_init(void) -{ - uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS); - uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - -static void baytrail_rtc_init(void) -{ - uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0); - uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32))); - int rtc_failed = !!(gen_pmcon1 & RPS); - - if (rtc_failed) { - printk(BIOS_DEBUG, - "RTC Failure detected. Resetting Date to %s\n", - coreboot_dmi_date); - - write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS); - } - - cmos_init(rtc_failed); -} - -/* Entry from cache-as-ram.inc. */ -void main(FSP_INFO_HEADER *fsp_info_header) -{ - uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS); - uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2); - uint32_t fd_mask = 0; - uint32_t fd2_mask = 0; - - post_code(0x40); - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - post_code(0x41); - tco_disable(); - - post_code(0x42); - if (CONFIG(ENABLE_BUILTIN_COM1)) - byt_config_com1_and_enable(); - - post_code(0x43); - console_init(); - - spi_init(); - baytrail_rtc_init(); - - /* Call into mainboard. */ - early_mainboard_romstage_entry(); - - set_max_freq(); - - post_code(0x44); - - /* Program any required function disables */ - get_func_disables(&fd_mask, &fd2_mask); - - if (fd_mask != 0) { - write32(func_dis, read32(func_dis) | fd_mask); - /* Ensure posted write hits. */ - read32(func_dis); - } - - if (fd2_mask != 0) { - write32(func_dis2, read32(func_dis2) | fd2_mask); - /* Ensure posted write hits. */ - read32(func_dis2); - } - - post_code(0x47); - - timestamp_add_now(TS_BEFORE_INITRAM); - - /* - * Call early init to initialize memory and chipset. This function returns - * to the romstage_main_continue function with a pointer to the HOB - * structure. - */ - post_code(0x48); - printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n"); - fsp_early_init(fsp_info_header); - die_with_post_code(POST_INVALID_VENDOR_BINARY, - "Uh Oh! fsp_early_init should not return here.\n"); -} - -/******************************************************************************* - * The FSP early_init function returns to this function. - * Memory is setup and the stack is set by the FSP. - */ -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) -{ - void *cbmem_hob_ptr; - uint32_t prev_sleep_state; - - timestamp_add_now(TS_AFTER_INITRAM); - - post_code(0x4a); - printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", - __func__, (u32) status, (u32) hob_list_ptr); - - /* FSP reconfigures USB, so reinit it to have debug */ - if (CONFIG(USBDEBUG_IN_PRE_RAM)) - usbdebug_hw_init(true); - - printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); - - /* Get previous sleep state again and clear */ - prev_sleep_state = chipset_prev_sleep_state(1); - printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state); - - report_platform_info(); - - post_code(0x4b); - - late_mainboard_romstage_entry(); - post_code(0x4c); - - cbmem_recovery(prev_sleep_state == ACPI_S3); - - /* Save the HOB pointer in CBMEM to be used in ramstage*/ - cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); - if (cbmem_hob_ptr == NULL) - die("Could not allocate cbmem for HOB pointer"); - *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; - post_code(0x4e); - - romstage_handoff_init(prev_sleep_state == ACPI_S3); - - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - - /* Load the ramstage. */ - post_code(0x4f); - run_ramstage(); - while (1); -} - -uint64_t get_initial_timestamp(void) -{ - return 0; -} - -int vboot_platform_is_resuming(void) -{ - return !!romstage_handoff_is_resume(); -} diff --git a/src/soc/intel/fsp_baytrail/romstage/uart.c b/src/soc/intel/fsp_baytrail/romstage/uart.c deleted file mode 100644 index dbd6e9df10..0000000000 --- a/src/soc/intel/fsp_baytrail/romstage/uart.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the legacy UART hardware. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c deleted file mode 100644 index 1a8fb4b6e6..0000000000 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> -#include <device/pci_def.h> -#include <elog.h> -#include <halt.h> - -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/nvs.h> - -/* GNVS needs to be set by coreboot initiating a software SMI. */ -static global_nvs_t *gnvs; -static int smm_initialized; - -int southbridge_io_trap_handler(int smif) -{ - switch (smif) { - case 0x32: - printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: - * On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - */ - gnvs->smif = 0; - return 1; /* IO trap handled */ - } - - /* Not handled */ - return 0; -} - -void southbridge_smi_set_eos(void) -{ - enable_smi(EOS); -} - -global_nvs_t *smm_get_gnvs(void) -{ - return gnvs; -} - -static void busmaster_disable_on_bus(int bus) -{ - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - pci_devfn_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } -} - -static void southbridge_smi_sleep(void) -{ - uint32_t reg32; - uint8_t slp_typ; - uint16_t pmbase = get_pmbase(); - - /* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); - - /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); - slp_typ = acpi_sleep_from_pm1(reg32); - - /* Do any mainboard sleep handling */ - mainboard_smi_sleep(slp_typ); - - /* Log S3, S4, and S5 entry */ - if (slp_typ >= ACPI_S3) - elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); - - /* Next, do the deed. - */ - - switch (slp_typ) { - case ACPI_S0: - printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); - break; - case ACPI_S1: - printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); - break; - case ACPI_S3: - printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - - /* Invalidate the cache before going to S3 */ - wbinvd(); - break; - case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; - case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - - /* Disable all GPE */ - disable_all_gpe(); - - /* also iterates over all bridges on bus 0 */ - busmaster_disable_on_bus(0); - break; - default: - printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); - break; - } - - /* Write back to the SLP register to cause the originally intended - * event again. We need to set BIT13 (SLP_EN) though to make the - * sleep happen. - */ - enable_pm1_control(SLP_EN); - - /* Make sure to stop executing code here for S3/S4/S5 */ - if (slp_typ >= ACPI_S3) - halt(); - - /* In most sleep states, the code flow of this function ends at - * the line above. However, if we entered sleep state S1 and wake - * up again, we will continue to execute code in this function. - */ - reg32 = inl(pmbase + PM1_CNT); - if (reg32 & SCI_EN) { - /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); - } -} - -/* - * Look for Synchronous IO SMI and use save state from that - * core in case we are not running on the same core that - * initiated the IO transaction. - */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) -{ - em64t100_smm_state_save_area_t *state; - int node; - - /* Check all nodes looking for the one that issued the IO */ - for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - - /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) - continue; - - return state; - } - - return NULL; -} - -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - -static void southbridge_smi_apmc(void) -{ - uint8_t reg8; - em64t100_smm_state_save_area_t *state; - - /* Emulate B2 register as the FADT / Linux expects it */ - - reg8 = inb(APM_CNT); - switch (reg8) { - case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "C-state control\n"); - break; - case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause - * some kind of race condition in Linux - * and causes a kernel oops - */ - printk(BIOS_DEBUG, "P-state control\n"); - break; - case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); - break; - case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); - printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); - break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; - case APM_CNT_ELOG_GSMI: - if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); - break; - } - - mainboard_smi_apmc(reg8); -} - -static void southbridge_smi_pm1(void) -{ - uint16_t pm1_sts = clear_pm1_status(); - - /* While OSPM is not active, poweroff immediately - * on a power button event. - */ - if (pm1_sts & PWRBTN_STS) { - // power button pressed - elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); - } -} - -static void southbridge_smi_gpe0(void) -{ - clear_gpe_status(); -} - -static void southbridge_smi_tco(void) -{ - uint32_t tco_sts = clear_tco_status(); - - /* Any TCO event? */ - if (!tco_sts) - return; - - if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ - /* Handle TCO timeout */ - printk(BIOS_DEBUG, "TCO Timeout.\n"); - } -} - -static void southbridge_smi_periodic(void) -{ - uint32_t reg32; - - reg32 = inl(get_pmbase() + SMI_EN); - - /* Are periodic SMIs enabled? */ - if ((reg32 & PERIODIC_EN) == 0) - return; - - printk(BIOS_DEBUG, "Periodic SMI.\n"); -} - -typedef void (*smi_handler_t)(void); - -static const smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - NULL, // [10] reserved - NULL, // [11] reserved - NULL, // [12] reserved - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - NULL, // [21] reserved - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] reserved - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] PUNIT - NULL, // [29] GUNIT - NULL, // [30] reserved - NULL // [31] reserved -}; - -void southbridge_smi_handler(void) -{ - int i; - uint32_t smi_sts; - - /* We need to clear the SMI status registers, or we won't see what's - * happening in the following calls. - */ - smi_sts = clear_smi_status(); - - /* Call SMI sub handler for each of the status bits */ - for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { - if (!(smi_sts & (1 << i))) - continue; - - if (southbridge_smi[i] != NULL) { - southbridge_smi[i](); - } else { - printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " - "handler available.\n", i); - } - } - - /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, - * these events need to be cleared and checked unconditionally. */ - mainboard_smi_gpi(clear_alt_status()); -} diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c deleted file mode 100644 index fbfd094c93..0000000000 --- a/src/soc/intel/fsp_baytrail/smm.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/smm_reloc.h> -#include <bootstate.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/pmc.h> - -/* Save the gpio route register. The settings are committed from - * smm_southbridge_enable_smi(). */ -static uint32_t gpio_route; - -void smm_southcluster_save_gpio_route(uint32_t route) -{ - gpio_route = route; -} - -void smm_southbridge_clear_state(void) -{ - uint32_t smi_en; - - /* Log events from chipset before clearing */ - if (CONFIG(ELOG)) - southcluster_log_state(); - - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); - - smi_en = inl(get_pmbase() + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); - clear_alt_status(); - clear_pmc_status(); -} - -static void smm_southcluster_route_gpios(void) -{ - u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); - const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; - uint32_t alt_gpio_reg = 0; - uint32_t route_reg = gpio_route; - int i; - - printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg); - - /* Start the routing for the specific gpios. */ - write32(gpio_rout, route_reg); - - /* Enable SMIs for the gpios that are set to trigger the SMI. */ - for (i = 0; i < 16; i++) { - if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { - alt_gpio_reg |= (1 << i); - } - route_reg >>= 2; - } - printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); - - outl(alt_gpio_reg, alt_gpio_smi); -} - -void smm_southbridge_enable_smi(void) -{ - - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events Disable pcie wake. */ - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - disable_gpe(PME_B0_EN); - - /* Set up the GPIO route. */ - smm_southcluster_route_gpios(); - - /* Enable SMI generation: - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on TCO events - * - on microcontroller writes (io 0x62/0x66) - */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); -} - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* - * Issue SMI to set the gnvs pointer in SMM. - * tcg and smi1 are unused. - * - * EAX = APM_CNT_GNVS_UPDATE - * EBX = gnvs pointer - * EDX = APM_CNT - */ - asm volatile ( - "outb %%al, %%dx\n\t" - : /* ignore result */ - : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), - "d" (APM_CNT) - ); -} - -static void finalize_chipset(void *unused) -{ - printk(BIOS_DEBUG, "Finalizing SMM.\n"); - /* Lock sleep stretching policy and set SMI lock. */ - write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2), - read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)) - | SLPSX_STR_POL_LOCK | SMI_LOCK); - outb(APM_CNT_FINALIZE, APM_CNT); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c deleted file mode 100644 index 59411ec5f8..0000000000 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ /dev/null @@ -1,616 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <arch/ioapic.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <pc80/i8254.h> -#include <pc80/i8259.h> -#include <pc80/isa-dma.h> - -#include <soc/baytrail.h> -#include <soc/iomap.h> -#include <soc/irq.h> -#include <soc/lpc.h> -#include <soc/nvs.h> -#include <soc/acpi.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/ramstage.h> -#include "chip.h" -#include <arch/acpi.h> - -typedef struct soc_intel_fsp_baytrail_config config_t; - -static inline void -add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) -{ - mmio_resource(dev, i, addr >> 10, size >> 10); -} - -static void sc_add_mmio_resources(struct device *dev) -{ - add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); - add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); - add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); - add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); - add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); - add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); - add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); - add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); - add_mmio_resource(dev, 0xfff, 0xffffffff - CONFIG_VIRTUAL_ROM_SIZE + 1, - CONFIG_VIRTUAL_ROM_SIZE); /* BIOS ROM */ - add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ -} - -/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ -#define LPC_DEFAULT_IO_RANGE_LOWER 0 -#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 - -static void sc_enable_ioapic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10); - u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); - - /* - * Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - write32(ilb_base + ILB_OIC, 0x100); /* AEN */ - reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ - write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - -static void sc_enable_serial_irqs(struct device *dev) -{ -#ifdef SETUPSERIQ /* NOT defined. Remove when the TODO is done. */ - /* - * TODO: SERIRQ seems to have a number of problems on baytrail. - * With it enabled, we get some spurious interrupts (ps2) - * in seabios. It also caused IOCHK# NMIs. Remove it - * until we understand how it needs to be configured. - */ - u8 reg8; - u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); - - /* - * Disable the IOCHK# NMI. Let the NMI handler enable it if it needs. - */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */ - outb(reg8, 0x61); - - write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); - write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); - -#if !CONFIG(SERIRQ_CONTINUOUS_MODE) - /* - * SoC requires that the System BIOS first set the SERIRQ logic to - * continuous mode operation for at least one frame before switching - * it into quiet mode operation. - */ - outb(0x00, 0xED); /* I/O Delay to get the 1 frame */ - write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE); -#endif -#endif /* DON'T SET UP IRQS */ -} - -/* - * Write PCI config space IRQ assignments. PCI devices have the INT_LINE - * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing - * information to operating systems and drivers. The INT_PIN register is - * generally read only and reports which interrupt pin A - D it uses. The - * INT_LINE register is configurable and reports which IRQ (generally the - * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling - * on devices that are downstream on a PCI bridge into account. - * - * This function will loop through all enabled PCI devices and program the - * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it - * uses. It then configures each interrupt in the pic to be level triggered. - */ -static void write_pci_config_irqs(void) -{ - struct device *irq_dev; - struct device *targ_dev; - uint8_t int_line = 0; - uint8_t original_int_pin = 0; - uint8_t new_int_pin = 0; - uint16_t current_bdf = 0; - uint16_t parent_bdf = 0; - uint8_t pirq = 0; - uint8_t device_num = 0; - const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - - if (ir == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" - " 'global_baytrail_irq_route' structure does not exist\n"); - return; - } - - /* - * Loop through all enabled devices and program their - * INT_LINE, INT_PIN registers from values taken from - * the Interrupt Route registers in the ILB - */ - printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - - if ((irq_dev->path.type != DEVICE_PATH_PCI) || - (!irq_dev->enabled)) - continue; - - current_bdf = irq_dev->path.pci.devfn | - irq_dev->bus->secondary << 8; - - /* - * Step 1: Get the INT_PIN and device structure to look for - * in the pirq_data table defined in the mainboard directory. - */ - targ_dev = NULL; - new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); - if (targ_dev == NULL || new_int_pin < 1) - continue; - - /* - * Adjust the INT routing for the PCIe root ports - * See 'Interrupt Generated for INT[A-D] Interrupts' - * Table 241 in Document Number: 538136, Rev. 3.9 - */ - if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV && - targ_dev != irq_dev) - new_int_pin = ((new_int_pin - 1 + - PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1; - - /* Get the original INT_PIN for record keeping */ - original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - parent_bdf = targ_dev->path.pci.devfn - | targ_dev->bus->secondary << 8; - device_num = PCI_SLOT(parent_bdf); - - if (ir->pcidev[device_num] == 0) { - printk(BIOS_WARNING, - "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", - device_num); - continue; - } - - /* Find the PIRQ that is attached to the INT_PIN this device uses */ - pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; - - /* Get the INT_LINE this device/function will use */ - int_line = ir->pic[pirq]; - - if (int_line != PIRQ_PIC_IRQDISABLE) { - /* Set this IRQ to level triggered since it is used by a PCI device */ - i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); - /* Set the Interrupt Line register in PCI config space */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } else { - /* Set the Interrupt line register as "unknown or unused" */ - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, - PIRQ_PIC_UNKNOWN_UNUSED); - } - - printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", - original_int_pin, pin_to_str(original_int_pin)); - if (parent_bdf != current_bdf) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - new_int_pin, pin_to_str(new_int_pin)); - printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" - "\tINT_LINE\t: 0x%X (IRQ %d)\n", - 'A' + pirq, int_line, int_line); - } - printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); -} - -static void sc_pirq_init(struct device *dev) -{ - int i, j; - int pirq; - u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); - u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); - u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); - const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - - /* Set up the PIRQ PIC routing based on static config. */ - printk(BIOS_SPEW, "Start writing IRQ assignments\n" - "PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n" - "IRQ "); - for (i = 0; i < NUM_PIRQS; i++) { - write8(pr_base + i, ir->pic[i]); - printk(BIOS_SPEW, "\t%d", ir->pic[i]); - } - printk(BIOS_SPEW, "\n\n"); - - /* Set up the per device PIRQ routing based on static config. */ - printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" - "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); - for (i = 0; i < NUM_OF_PCI_DEVS; i++) { - write16(ir_base + i, ir->pcidev[i]); - - /* If the entry is more than just 0, print it out */ - if (ir->pcidev[i]) { - printk(BIOS_SPEW, " %d: ", i); - for (j = 0; j < 4; j++) { - pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; - printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); - } - printk(BIOS_SPEW, "\n"); - } - } - - /* Route SCI to IRQ9 */ - write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); - printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); - - /* Write IRQ assignments to PCI config space */ - write_pci_config_irqs(); -} - -static inline int io_range_in_default(int base, int size) -{ - /* Does it start above the range? */ - if (base >= LPC_DEFAULT_IO_RANGE_UPPER) - return 0; - - /* Is it entirely contained? */ - if (base >= LPC_DEFAULT_IO_RANGE_LOWER && - (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) - return 1; - - /* This will return not in range for partial overlaps. */ - return 0; -} - -/* - * Note: this function assumes there is no overlap with the default LPC device's - * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. - */ -static void sc_add_io_resource(struct device *dev, int base, int size, int index) -{ - struct resource *res; - - if (io_range_in_default(base, size)) - return; - - res = new_resource(dev, index); - res->base = base; - res->size = size; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED; -} - -static void sc_add_io_resources(struct device *dev) -{ - struct resource *res; - u8 io_index = 0; - - /* - * Add the default claimed IO range for the LPC device - * and mark it as subtractive decode. - */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = LPC_DEFAULT_IO_RANGE_LOWER; - res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* GPIO */ - sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); - - /* ACPI */ - sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); -} - -static void sc_read_resources(struct device *dev) -{ - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add non-standard MMIO resources. */ - sc_add_mmio_resources(dev); - - /* Add IO resources. */ - sc_add_io_resources(dev); -} - -static void enable_hpet(void) -{ -} - -static void sc_init(struct device *dev) -{ - u8 *ibase; - - printk(BIOS_DEBUG, "soc: southcluster_init\n"); - - ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); - - write8(ibase + ILB_MC, 0); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); - - /* IO APIC initialization. */ - sc_enable_ioapic(dev); - - sc_enable_serial_irqs(dev); - - /* Setup the PIRQ. */ - sc_pirq_init(dev); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); - - /* Initialize ISA DMA. */ - isa_dma_init(); - - setup_i8259(); - - setup_i8254(); -} - -/* - * Common code for the south cluster devices. - */ - -/* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(struct device *dev) -{ - u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); - u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); - uint32_t fd_mask = 0; - uint32_t fd2_mask = 0; - -#define SET_DIS_MASK(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - fd_mask |= name_ ## _DIS -#define SET_DIS_MASK2(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - fd2_mask |= name_ ## _DIS - - switch (dev->path.pci.devfn) { - SET_DIS_MASK(LPE); - break; - SET_DIS_MASK(TXE); - break; - SET_DIS_MASK(PCIE_PORT1); - break; - SET_DIS_MASK(PCIE_PORT2); - break; - SET_DIS_MASK(PCIE_PORT3); - break; - SET_DIS_MASK(PCIE_PORT4); - break; - SET_DIS_MASK2(SMBUS); - break; - SET_DIS_MASK(OTG); - /* Disable OTG PHY when OTG is not available. */ - fd2_mask |= OTG_SS_PHY_DIS; - break; - } - - if (fd_mask != 0) { - write32(func_dis, read32(func_dis) | fd_mask); - /* Ensure posted write hits. */ - read32(func_dis); - } - - if (fd2_mask != 0) { - write32(func_dis2, read32(func_dis2) | fd2_mask); - /* Ensure posted write hits. */ - read32(func_dis2); - } -} - -static inline void set_d3hot_bits(struct device *dev, int offset) -{ - uint32_t reg8; - printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); - reg8 = pci_read_config8(dev, offset + 4); - reg8 |= 0x3; - pci_write_config8(dev, offset + 4, reg8); -} - -/* Parts of the audio subsystem are powered by the HDA device. Therefore, one - * cannot put HDA into D3Hot. Instead perform this workaround to make some of - * the audio paths work for LPE audio. */ -static void hda_work_around(struct device *dev) -{ - u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); - - /* Need to set magic register 0x43 to 0xd7 in config space. */ - pci_write_config8(dev, 0x43, 0xd7); - - /* Need to set bit 0 of GCTL to take the device out of reset. However, - * that requires setting up the 64-bit BAR. */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - write32(gctl, read32(gctl) | 0x1); - pci_write_config8(dev, PCI_COMMAND, 0); - pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); -} - -static int place_device_in_d3hot(struct device *dev) -{ - unsigned int offset; - - /* Parts of the HDA block are used for LPE audio as well. - * Therefore assume the HDA will never be put into D3Hot. */ - if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { - hda_work_around(dev); - return 0; - } - - offset = pci_find_capability(dev, PCI_CAP_ID_PM); - - if (offset != 0) { - set_d3hot_bits(dev, offset); - return 0; - } - - /* For some reason some of the devices don't have the capability - * pointer set correctly. Work around this by hard coding the offset. */ -#define DEV_CASE(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - - switch (dev->path.pci.devfn) { - DEV_CASE(MIPI): - DEV_CASE(SDIO): - DEV_CASE(EMMC): - DEV_CASE(SD): - DEV_CASE(MMC45): - DEV_CASE(LPE): - DEV_CASE(SIO_DMA1): - DEV_CASE(I2C1): - DEV_CASE(I2C2): - DEV_CASE(I2C3): - DEV_CASE(I2C4): - DEV_CASE(I2C5): - DEV_CASE(I2C6): - DEV_CASE(I2C7): - DEV_CASE(SIO_DMA2): - DEV_CASE(PWM1): - DEV_CASE(PWM2): - DEV_CASE(HSUART1): - DEV_CASE(HSUART2): - DEV_CASE(SPI): - DEV_CASE(OTG): - offset = 0x80; - break; - DEV_CASE(SATA): - DEV_CASE(XHCI): - DEV_CASE(EHCI): - offset = 0x70; - break; - DEV_CASE(HDA): - DEV_CASE(SMBUS): - offset = 0x50; - break; - DEV_CASE(TXE): - /* TXE cannot be placed in D3Hot. */ - return 0; - break; - DEV_CASE(PCIE_PORT1): - DEV_CASE(PCIE_PORT2): - DEV_CASE(PCIE_PORT3): - DEV_CASE(PCIE_PORT4): - offset = 0xa0; - break; - } - - if (offset != 0) { - set_d3hot_bits(dev, offset); - return 0; - } - - return -1; -} - -/* Common PCI device function disable. */ -void southcluster_enable_dev(struct device *dev) -{ - uint32_t reg32; - - if (!dev->enabled) { - int slot = PCI_SLOT(dev->path.pci.devfn); - int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", - dev_path(dev), slot, func); - - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Place device in D3Hot */ - if (place_device_in_d3hot(dev) < 0) { - printk(BIOS_WARNING, - "Could not place %02x.%01x into D3Hot. " - "Keeping device visible.\n", slot, func); - return; - } - /* Disable this device if possible */ - sc_disable_devfn(dev); - } else { - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); - } -} - -static struct device_operations device_ops = { - .read_resources = sc_read_resources, - .set_resources = pci_dev_set_resources, - .acpi_inject_dsdt_generator = southcluster_inject_dsdt, - .write_acpi_tables = southcluster_write_acpi_tables, - .enable_resources = NULL, - .init = sc_init, - .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = LPC_DEVID, -}; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c deleted file mode 100644 index 8aa6290386..0000000000 --- a/src/soc/intel/fsp_baytrail/spi.c +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ -#include <arch/early_variables.h> -#include <stdint.h> -#include <stdlib.h> -#include <commonlib/helpers.h> -#include <delay.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <spi_flash.h> -#include <spi-generic.h> - -#include <soc/lpc.h> -#include <soc/pci_devs.h> - -typedef struct spi_slave ich_spi_slave; - -static int g_ichspi_lock CAR_GLOBAL = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint8_t _reserved3[16]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; -} ich_spi_controller; - -static ich_spi_controller g_cntlr CAR_GLOBAL; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#define SPI_OFFSET_MASK 0x3ff - -static uint8_t readb_(const void *addr) -{ - uint8_t v = read8(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static uint16_t readw_(const void *addr) -{ - uint16_t v = read16(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static uint32_t readl_(const void *addr) -{ - uint32_t v = read32(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static void writeb_(uint8_t b, void *addr) -{ - write8(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void writew_(uint16_t b, void *addr) -{ - write16(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void writel_(uint32_t b, void *addr) -{ - write32(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) - -void spi_init(void) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - ich9_spi_regs *ich9_spi = spi_regs(); - - car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); - cntlr->opmenu = ich9_spi->opmenu; - cntlr->menubytes = sizeof(ich9_spi->opmenu); - cntlr->optype = &ich9_spi->optype; - cntlr->addr = &ich9_spi->faddr; - cntlr->data = (uint8_t *)ich9_spi->fdata; - cntlr->databytes = sizeof(ich9_spi->fdata); - cntlr->status = &ich9_spi->ssfs; - cntlr->control = (uint16_t *)ich9_spi->ssfc; - cntlr->preop = &ich9_spi->preop; -} - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint16_t optypes; - uint8_t opmenu[MENU_BYTES]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!car_get_var(g_ichspi_lock)) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr->opmenu); - optypes = readw_(cntlr->optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr->optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == ARRAY_SIZE(opmenu)) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr->optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(uint16_t bitmask, int wait_til_set) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - int timeout = 40000; /* This will result in 400 ms */ - uint16_t status = 0; - - while (timeout--) { - status = readw_(cntlr->status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr->status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); - - spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) - return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) - return -1; - - if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - writew_(trans.opcode, cntlr->preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr->preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr->control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - goto spi_xfer_exit; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr->databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr->databytes); - else - data_length = min(trans.bytesin, cntlr->databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr->data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr->databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr->control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr->data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - -spi_xfer_exit: - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr->preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c deleted file mode 100644 index d31ddd9be3..0000000000 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include <soc/msr.h> -#include <soc/baytrail.h> - -unsigned int bus_freq_khz(void) -{ - msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - switch (clk_info.lo & 0x3) { - case 0: - return 83333; - case 1: - return 100000; - case 2: - return 133333; - case 3: - return 116666; - default: - return 0; - } -} - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - unsigned int bclk_khz = bus_freq_khz(); - - if (!bclk_khz) - return 0; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; -} - -void set_max_freq(void) -{ - msr_t perf_ctl; - msr_t msr; - - /* Enable speed step. */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 16); - wrmsr(IA32_MISC_ENABLE, msr); - - /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of - * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_RATIOS); - perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; - /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of - * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_VIDS); - perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; - perf_ctl.hi = 0; - - wrmsr(IA32_PERF_CTL, perf_ctl); -} |