diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-11-03 22:52:04 +0100 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-11-09 15:47:04 +0000 |
| commit | d92bb3c3f1447e6731a9694f16338c48e5d9f954 (patch) | |
| tree | bc85c91a0f6a2377d60b6e9234637730d0c17a21 /src/soc | |
| parent | 600fa266bdc8740126420e63579a5b9d103ca960 (diff) | |
soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
This aligns Picasso more with the newer AMD SoCs and also makes it a bit
clearer what this file does. Also remove the unneeded tabs at the
beginning of each line.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/acpi/pci_int_defs.asl | 65 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/pcie.asl | 65 |
2 files changed, 65 insertions, 65 deletions
diff --git a/src/soc/amd/picasso/acpi/pci_int_defs.asl b/src/soc/amd/picasso/acpi/pci_int_defs.asl new file mode 100644 index 0000000000..0e1a5b6393 --- /dev/null +++ b/src/soc/amd/picasso/acpi/pci_int_defs.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PCI IRQ mapping registers, C00h-C01h. */ +OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ +} +IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + Offset (0x43), + PMMC, 0x00000008, /* Index 0x43: eMMC */ + + Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PI25, 0x00000008, /* Index 0x77: I2C5 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xC3), + IMMC, 0x00000008, /* Index 0xC3: eMMC */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + II25, 0x00000008, /* Index 0xF7: I2C5 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ +} diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl deleted file mode 100644 index 601de5247e..0000000000 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* PCI IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0: INTA */ - PIRB, 0x00000008, /* Index 1: INTB */ - PIRC, 0x00000008, /* Index 2: INTC */ - PIRD, 0x00000008, /* Index 3: INTD */ - PIRE, 0x00000008, /* Index 4: INTE */ - PIRF, 0x00000008, /* Index 5: INTF */ - PIRG, 0x00000008, /* Index 6: INTG */ - PIRH, 0x00000008, /* Index 7: INTH */ - - Offset (0x43), - PMMC, 0x00000008, /* Index 0x43: eMMC */ - - Offset (0x62), - PGPI, 0x00000008, /* Index 0x62: GPIO */ - - Offset (0x70), - PI20, 0x00000008, /* Index 0x70: I2C0 */ - PI21, 0x00000008, /* Index 0x71: I2C1 */ - PI22, 0x00000008, /* Index 0x72: I2C2 */ - PI23, 0x00000008, /* Index 0x73: I2C3 */ - PUA0, 0x00000008, /* Index 0x74: UART0 */ - PUA1, 0x00000008, /* Index 0x75: UART1 */ - PI24, 0x00000008, /* Index 0x76: I2C4 */ - PI25, 0x00000008, /* Index 0x77: I2C5 */ - PUA2, 0x00000008, /* Index 0x78: UART2 */ - PUA3, 0x00000008, /* Index 0x79: UART3 */ - - /* IO-APIC IRQs */ - Offset (0x80), - IORA, 0x00000008, /* Index 0x80: INTA */ - IORB, 0x00000008, /* Index 0x81: INTB */ - IORC, 0x00000008, /* Index 0x82: INTC */ - IORD, 0x00000008, /* Index 0x83: INTD */ - IORE, 0x00000008, /* Index 0x84: INTE */ - IORF, 0x00000008, /* Index 0x85: INTF */ - IORG, 0x00000008, /* Index 0x86: INTG */ - IORH, 0x00000008, /* Index 0x87: INTH */ - - Offset (0xC3), - IMMC, 0x00000008, /* Index 0xC3: eMMC */ - - Offset (0xE2), - IGPI, 0x00000008, /* Index 0xE2: GPIO */ - - Offset (0xF0), - II20, 0x00000008, /* Index 0xF0: I2C0 */ - II21, 0x00000008, /* Index 0xF1: I2C1 */ - II22, 0x00000008, /* Index 0xF2: I2C2 */ - II23, 0x00000008, /* Index 0xF3: I2C3 */ - IUA0, 0x00000008, /* Index 0xF4: UART0 */ - IUA1, 0x00000008, /* Index 0xF5: UART1 */ - II24, 0x00000008, /* Index 0xF6: I2C4 */ - II25, 0x00000008, /* Index 0xF7: I2C5 */ - IUA2, 0x00000008, /* Index 0xF8: UART2 */ - IUA3, 0x00000008, /* Index 0xF9: UART3 */ - } |