diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-01-30 17:23:46 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-02-03 19:01:21 +0000 |
| commit | cfd6f9c7f1238c71b78273798c62d2f51cb5a555 (patch) | |
| tree | 9d4d3206c6cf6c7224dd3ed38b2bac18f0d6db13 /src/soc | |
| parent | 8c127ecc3c28a3188490af8daef43d528560ebd2 (diff) | |
soc/intel/alderlake: Add a few missing definitions in iomap.h
Some reserved address range listed in Alder Lake Platform Firmware
Architecture Specification document 626540 section 6.4 ADL - System
Memory Map such as North TraceHub ranges were missing. Details about
North TraceHub (aka. Intel TraceHub) can be found in Intel Trace
Hub (Intel TH) Developer's Manual document 671536.
BUG=b:264648959
TEST=Compilation successful
Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/iomap.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 0c332be2b6..6dd3bec140 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -23,6 +23,22 @@ #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 +/* North (Intel) TraceHub Software. */ +#define NTH_SW_BASE_ADDRESS 0xfc000000 +#define NTH_SW_BASE_SIZE 0x800000 + +/* North (Intel) TraceHub Firmware. */ +#define NTH_FW_BASE_ADDRESS 0xfae00000 +#define NTH_FW_BASE_SIZE 0x200000 + +/* North (Intel) TraceHub Memory storage controller Trace Buffer. */ +#define NTH_MTB_BASE_ADDRESS 0xfad00000 +#define NTH_MTB_BASE_SIZE 0x100000 + +/* North (Intel) TraceHub Real Time Instruction Trace. */ +#define NTH_RTIT_BASE_ADDRESS 0xfacfc000 +#define NTH_RTIT_BASE_SIZE 0x4000 + #define UART_BASE_SIZE 0x1000 #define UART_BASE_0_ADDRESS 0xfe03e000 |